SG129396A1 - Method for machining a semiconductor wafer on bothsides in a carrier, carrier and a semiconductor w afer produced by the method - Google Patents

Method for machining a semiconductor wafer on bothsides in a carrier, carrier and a semiconductor w afer produced by the method

Info

Publication number
SG129396A1
SG129396A1 SG200604776A SG200604776A SG129396A1 SG 129396 A1 SG129396 A1 SG 129396A1 SG 200604776 A SG200604776 A SG 200604776A SG 200604776 A SG200604776 A SG 200604776A SG 129396 A1 SG129396 A1 SG 129396A1
Authority
SG
Singapore
Prior art keywords
carrier
semiconductor wafer
machining
semiconductor
inlay
Prior art date
Application number
SG200604776A
Other languages
English (en)
Inventor
Rudiger Dr Schmolke
Thomas Buschhardt
Gerhard Heier
Guido Dr Wenski
Original Assignee
Siltronic Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic Ag filed Critical Siltronic Ag
Publication of SG129396A1 publication Critical patent/SG129396A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/28—Work carriers for double side lapping of plane surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
SG200604776A 2005-07-21 2006-07-17 Method for machining a semiconductor wafer on bothsides in a carrier, carrier and a semiconductor w afer produced by the method SG129396A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102005034119A DE102005034119B3 (de) 2005-07-21 2005-07-21 Verfahren zum Bearbeiten einer Halbleiterscheibe, die in einer Aussparung einer Läuferscheibe geführt wird

Publications (1)

Publication Number Publication Date
SG129396A1 true SG129396A1 (en) 2007-02-26

Family

ID=37402214

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200604776A SG129396A1 (en) 2005-07-21 2006-07-17 Method for machining a semiconductor wafer on bothsides in a carrier, carrier and a semiconductor w afer produced by the method

Country Status (7)

Country Link
US (1) US7541287B2 (ko)
JP (1) JP4395495B2 (ko)
KR (1) KR100856516B1 (ko)
CN (1) CN100511598C (ko)
DE (1) DE102005034119B3 (ko)
SG (1) SG129396A1 (ko)
TW (1) TWI330866B (ko)

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JP5245319B2 (ja) 2007-08-09 2013-07-24 富士通株式会社 研磨装置及び研磨方法、基板及び電子機器の製造方法
KR100898821B1 (ko) * 2007-11-29 2009-05-22 주식회사 실트론 웨이퍼 캐리어의 제조방법
JP4858507B2 (ja) * 2008-07-31 2012-01-18 トーカロ株式会社 被研磨物保持用キャリア
JP2010036288A (ja) * 2008-08-01 2010-02-18 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 研磨用治具
KR101026574B1 (ko) * 2009-01-08 2011-03-31 주식회사 엘지실트론 양면 연마 장치용 캐리어와 프레이트 및 이를 이용한 양면 연마 장치
DE102009022223A1 (de) 2009-05-20 2010-11-25 Siltronic Ag Verfahren zur Bildung eines Läuferscheibensatzes
JP5452984B2 (ja) * 2009-06-03 2014-03-26 不二越機械工業株式会社 ウェーハの両面研磨方法
DE102009025243B4 (de) 2009-06-17 2011-11-17 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe aus Silicium
JP5233888B2 (ja) * 2009-07-21 2013-07-10 信越半導体株式会社 両面研磨装置用キャリアの製造方法、両面研磨装置用キャリア及びウェーハの両面研磨方法
US8952496B2 (en) * 2009-12-24 2015-02-10 Sumco Corporation Semiconductor wafer and method of producing same
KR101597158B1 (ko) * 2012-06-25 2016-02-24 가부시키가이샤 사무코 워크의 연마 방법 및 워크의 연마 장치
JP5748717B2 (ja) 2012-09-06 2015-07-15 信越半導体株式会社 両面研磨方法
DE102013218880A1 (de) * 2012-11-20 2014-05-22 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe, umfassend das gleichzeitige Polieren einer Vorderseite und einer Rückseite einer Substratscheibe
JP6206942B2 (ja) * 2012-12-28 2017-10-04 株式会社グローバルアイ 円盤状キャリア
DE102013200756A1 (de) 2013-01-18 2014-08-07 Siltronic Ag Läuferscheibe für die beidseitige Politur von Scheiben aus Halbleitermaterial
JP2014188668A (ja) * 2013-03-28 2014-10-06 Hoya Corp ガラス基板の製造方法
CN107431034A (zh) * 2015-03-11 2017-12-01 贝卡尔特公司 用于临时键合晶片的载体
JP6443370B2 (ja) * 2016-03-18 2018-12-26 信越半導体株式会社 両面研磨装置用のキャリアの製造方法およびウェーハの両面研磨方法
SG11201802381PA (en) * 2016-03-31 2018-04-27 Hoya Corp Carrier and substrate manufacturing method using this carrier
CN107127674B (zh) * 2017-07-08 2021-01-08 上海致领半导体科技发展有限公司 一种用于半导体晶片抛光的陶瓷载盘
CN108682613B (zh) * 2018-03-29 2021-02-26 广东先导先进材料股份有限公司 半导体晶片的处理方法
KR102131443B1 (ko) * 2018-10-04 2020-07-08 주식회사 이포스 연마장치용 캐리어
CN110193775B (zh) * 2019-03-12 2021-09-17 上海新昇半导体科技有限公司 化学机械抛光方法以及化学抛光系统
CN111993267B (zh) * 2019-05-27 2024-08-06 创技股份有限公司 工件游星轮及工件游星轮的制造方法
CN113510614A (zh) * 2021-08-03 2021-10-19 菲特晶(南京)电子有限公司 一种双面研磨机用游轮结构
CN115990825A (zh) * 2022-12-27 2023-04-21 西安奕斯伟材料科技股份有限公司 一种硅片双面抛光用的载具、双面抛光装置及硅片
CN115816267A (zh) * 2022-12-29 2023-03-21 西安奕斯伟材料科技有限公司 硅片双面抛光装置的承载件及硅片双面抛光装置

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EP1489649A1 (en) * 2002-03-28 2004-12-22 Shin-Etsu Handotai Co., Ltd Double side polishing device for wafer and double side polishing method
JP2004047801A (ja) 2002-07-12 2004-02-12 Sumitomo Mitsubishi Silicon Corp 半導体ウエーハの研磨方法
DE10250823B4 (de) * 2002-10-31 2005-02-03 Siltronic Ag Läuferscheibe und Verfahren zur gleichzeitig beidseitigen Bearbeitung von Werkstücken
DE10322181B4 (de) * 2003-05-16 2005-05-25 The Gleason Works Abrichtwerkzeug zum Abrichten einer Schleifschnecke
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WO2006013996A1 (en) * 2004-08-02 2006-02-09 Showa Denko K.K. Method of manufacturing polishing carrier and silicon substrate for magnetic recording medium, and silicon substrate for magnetic recording medium

Also Published As

Publication number Publication date
TWI330866B (en) 2010-09-21
CN1901142A (zh) 2007-01-24
JP4395495B2 (ja) 2010-01-06
US20070021042A1 (en) 2007-01-25
JP2007036225A (ja) 2007-02-08
CN100511598C (zh) 2009-07-08
KR100856516B1 (ko) 2008-09-04
DE102005034119B3 (de) 2006-12-07
TW200705562A (en) 2007-02-01
KR20070012230A (ko) 2007-01-25
US7541287B2 (en) 2009-06-02

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