SG10201803196YA - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the sameInfo
- Publication number
- SG10201803196YA SG10201803196YA SG10201803196YA SG10201803196YA SG10201803196YA SG 10201803196Y A SG10201803196Y A SG 10201803196YA SG 10201803196Y A SG10201803196Y A SG 10201803196YA SG 10201803196Y A SG10201803196Y A SG 10201803196YA SG 10201803196Y A SG10201803196Y A SG 10201803196YA
- Authority
- SG
- Singapore
- Prior art keywords
- layer
- channel
- disposed
- channel hole
- fabricating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000010410 layer Substances 0.000 abstract 12
- 238000002161 passivation Methods 0.000 abstract 4
- 239000011229 interlayer Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/145—Read-only memory [ROM]
- H01L2924/1451—EPROM
- H01L2924/14511—EEPROM
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170085703A KR102373616B1 (ko) | 2017-07-06 | 2017-07-06 | 반도체 장치 및 그 제조 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201803196YA true SG10201803196YA (en) | 2019-02-27 |
Family
ID=64903478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201803196YA SG10201803196YA (en) | 2017-07-06 | 2018-04-17 | Semiconductor device and method for fabricating the same |
Country Status (4)
Country | Link |
---|---|
US (2) | US10340284B2 (ko) |
KR (1) | KR102373616B1 (ko) |
CN (1) | CN109216365B (ko) |
SG (1) | SG10201803196YA (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2019165171A (ja) * | 2018-03-20 | 2019-09-26 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
KR20200115769A (ko) * | 2019-03-25 | 2020-10-08 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
KR20200141257A (ko) * | 2019-06-10 | 2020-12-18 | 에스케이하이닉스 주식회사 | 메모리 장치 및 그 제조 방법 |
WO2021035572A1 (en) * | 2019-08-28 | 2021-03-04 | Yangtze Memory Technologies Co., Ltd. | Semiconductor device and fabricating method thereof |
KR20210054788A (ko) | 2019-11-06 | 2021-05-14 | 에스케이하이닉스 주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
KR102578390B1 (ko) * | 2020-11-17 | 2023-09-14 | 한양대학교 산학협력단 | 에어 갭을 포함하는 3차원 플래시 메모리 및 그 제조 방법 |
KR102497881B1 (ko) * | 2020-10-29 | 2023-02-10 | 한양대학교 산학협력단 | 집적도를 향상시킨 3차원 플래시 메모리 및 그 동작 방법 |
KR102556381B1 (ko) * | 2021-01-28 | 2023-07-17 | 한양대학교 산학협력단 | 단순화된 제조 공정을 통해 제조되는 3차원 플래시 메모리 및 그 제조 방법 |
CN113053808B (zh) * | 2021-03-18 | 2022-06-17 | 长鑫存储技术有限公司 | 半导体结构制作方法及半导体结构 |
WO2022234614A1 (ja) * | 2021-05-06 | 2022-11-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
TWI775534B (zh) * | 2021-07-16 | 2022-08-21 | 旺宏電子股份有限公司 | 三維及式快閃記憶體及其形成方法 |
CN116259606B (zh) * | 2023-05-15 | 2023-08-11 | 之江实验室 | Tsv结构及其制备方法 |
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KR101624975B1 (ko) * | 2009-11-17 | 2016-05-30 | 삼성전자주식회사 | 3차원 반도체 기억 소자 |
US8455940B2 (en) * | 2010-05-24 | 2013-06-04 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, method of manufacturing the nonvolatile memory device, and memory module and system including the nonvolatile memory device |
KR101778287B1 (ko) * | 2010-08-30 | 2017-09-14 | 삼성전자주식회사 | 반도체 메모리 소자 및 그 제조방법 |
JP5543950B2 (ja) | 2011-09-22 | 2014-07-09 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法及び不揮発性半導体記憶装置 |
KR20130057670A (ko) * | 2011-11-24 | 2013-06-03 | 삼성전자주식회사 | 반도체 메모리 소자 및 그 제조방법 |
KR20130066950A (ko) * | 2011-12-13 | 2013-06-21 | 에스케이하이닉스 주식회사 | 3차원 불휘발성 메모리 소자와, 이를 포함하는 메모리 시스템과, 그 제조방법 |
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WO2014089795A1 (zh) | 2012-12-13 | 2014-06-19 | 中国科学院微电子研究所 | 一种垂直沟道型三维半导体存储器件及其制备方法 |
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KR102128465B1 (ko) | 2014-01-03 | 2020-07-09 | 삼성전자주식회사 | 수직 구조의 비휘발성 메모리 소자 |
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KR102175763B1 (ko) * | 2014-04-09 | 2020-11-09 | 삼성전자주식회사 | 반도체 메모리 장치 및 이의 제조 방법 |
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KR20160004069A (ko) | 2014-07-02 | 2016-01-12 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
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US9515085B2 (en) | 2014-09-26 | 2016-12-06 | Sandisk Technologies Llc | Vertical memory device with bit line air gap |
US9443865B2 (en) | 2014-12-18 | 2016-09-13 | Sandisk Technologies Llc | Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel |
KR20160087479A (ko) | 2015-01-13 | 2016-07-22 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
US9437611B1 (en) * | 2015-02-24 | 2016-09-06 | Macronix International Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9524980B2 (en) | 2015-03-03 | 2016-12-20 | Macronix International Co., Ltd. | U-shaped vertical thin-channel memory |
TWI541984B (zh) * | 2015-04-17 | 2016-07-11 | 旺宏電子股份有限公司 | 半導體結構及其製造方法 |
KR102282139B1 (ko) * | 2015-05-12 | 2021-07-28 | 삼성전자주식회사 | 반도체 장치 |
KR20170006978A (ko) | 2015-07-10 | 2017-01-18 | 에스케이하이닉스 주식회사 | 반도체 장치의 제조방법 |
US9627397B2 (en) * | 2015-07-20 | 2017-04-18 | Macronix International Co., Ltd. | Memory device and method for fabricating the same |
US9484353B1 (en) | 2015-07-20 | 2016-11-01 | Macronix International Co., Ltd. | Memory device and method for fabricating the same |
CN106571368B (zh) * | 2015-10-08 | 2022-01-25 | 三星电子株式会社 | 半导体装置 |
TWI582964B (zh) | 2015-12-30 | 2017-05-11 | 旺宏電子股份有限公司 | 記憶體元件及其製作方法 |
KR20180012640A (ko) * | 2016-07-27 | 2018-02-06 | 삼성전자주식회사 | 수직형 메모리 소자 및 이의 제조방법 |
US9679913B1 (en) * | 2016-11-04 | 2017-06-13 | Macronix International Co., Ltd. | Memory structure and method for manufacturing the same |
KR102665676B1 (ko) * | 2016-12-19 | 2024-05-14 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR20180073161A (ko) * | 2016-12-22 | 2018-07-02 | 삼성전자주식회사 | 수직형 메모리 장치 |
US10410931B2 (en) * | 2017-01-09 | 2019-09-10 | Samsung Electronics Co., Ltd. | Fabricating method of nanosheet transistor spacer including inner spacer |
US10403637B2 (en) * | 2017-01-20 | 2019-09-03 | Macronix International Co., Ltd. | Discrete charge trapping elements for 3D NAND architecture |
-
2017
- 2017-07-06 KR KR1020170085703A patent/KR102373616B1/ko active IP Right Grant
-
2018
- 2018-01-14 US US15/871,059 patent/US10340284B2/en active Active
- 2018-04-17 SG SG10201803196YA patent/SG10201803196YA/en unknown
- 2018-07-05 CN CN201810729739.4A patent/CN109216365B/zh active Active
-
2019
- 2019-07-01 US US16/459,337 patent/US10600806B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN109216365A (zh) | 2019-01-15 |
CN109216365B (zh) | 2023-10-17 |
US20190013328A1 (en) | 2019-01-10 |
KR20190005293A (ko) | 2019-01-16 |
KR102373616B1 (ko) | 2022-03-11 |
US10600806B2 (en) | 2020-03-24 |
US20190326321A1 (en) | 2019-10-24 |
US10340284B2 (en) | 2019-07-02 |
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