KR980006563A - 리드 온 칩 타입의 리드프레임 - Google Patents

리드 온 칩 타입의 리드프레임 Download PDF

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Publication number
KR980006563A
KR980006563A KR1019960023268A KR19960023268A KR980006563A KR 980006563 A KR980006563 A KR 980006563A KR 1019960023268 A KR1019960023268 A KR 1019960023268A KR 19960023268 A KR19960023268 A KR 19960023268A KR 980006563 A KR980006563 A KR 980006563A
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South Korea
Prior art keywords
lead
chip
pad
extending
chip type
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KR1019960023268A
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English (en)
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KR100224770B1 (ko
Inventor
강신영
김흥석
권정태
Original Assignee
김주용
현대전자산업주식회사
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Priority to KR1019960023268A priority Critical patent/KR100224770B1/ko
Priority to TW086107041A priority patent/TW384533B/zh
Priority to US08/863,307 priority patent/US5907186A/en
Priority to JP9155161A priority patent/JP2866362B2/ja
Priority to CN97111828A priority patent/CN1073283C/zh
Publication of KR980006563A publication Critical patent/KR980006563A/ko
Application granted granted Critical
Publication of KR100224770B1 publication Critical patent/KR100224770B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

본 발명은 리드 온 칩(lead on chip) 타입의 리드프레임에 관한 것으로, 리드 온 칩 타입에서 좌측패드과 우측패드를 가로지르는 리드를 번갈아가면서 형성하여 패키지의 면적을 최소화 할수 있는 것이다. 또한, 본 발명에 의한 리드 프레임을 사용하는 경우 칩의 좌우에 독립적인 회로 소자를 분리하여 제조할수가 있으며, 좌우에 있는 블럭 중에 어느 한쪽이 불량이 발생되는 경우에도 다른 쪽의 블럭은 사용할 수가 있다.

Description

리드 온 칩 타입의 리드프레임
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 실시예에 의해 제조된 리드 온 칩 타입의 리드프레임을 칩에 올려 놓은 것을 도시한 도면.

Claims (5)

  1. 칩의 중앙부에서 좌측에 위치에 종 방향으로 일정 간격으로 이격되면서 배열되는 다수의 좌측 패드들중에 번갈아가면서 좌측 패드에서 인접되는 위치에 리드의 단부가 위치하고, 우측 패드를 사이를 지나 칩의 우측 방향으로 연장되는 리드, 상기 칩의 중앙부에서 우측의 위치에 종 방향으로 일정 간격으로 이격되면서 배열되는 다수의 우측 패드를 중에서 상기 우측 방향으로 연장되는 리드에 와이어 본딩되지 않는 우측 패드에서 인접되는 위치에 리드의 단부가 위치하고, 상기 좌측 패드를 사이를 지나 칩의 좌측방향으로 연장되는 리드를 구비하는 것을 특징으로 하는 리드 온 칩 타입의 리드프레임.
  2. 제1항에 있어서, 상기 우측 방향으로 연장되는 리드와 좌측방향으로 연장되는 리드가 하나씩 걸러 반복적으로 배열 된 것을 특징으로 하는 리드 온 칩 타입의 리드프레임.
  3. 제1항에 있어서, 상기 우측방향으로 연장되는 리드와 촤측방향으로 연장되는 리드가 어떤지역에서는 하나씩 걸려 반복 배열되고, 다른 지역에서는 두개 또는 세개씩 걸려 반복 배열되는 것을 특징으로 하는 리드 온칩 타입의 리드프레임.
  4. 제1항에 있어서, 상기 칩의 좌측패드과 대응되는 우측 패드는 인접된 하나의 리드에 와이어 본딩 되도록 설계된 것을 특징으로 하는 리드 온 칩 타입의 리드프레임.
  5. 제1항에 있어서, 상기 칩은 좌우에 각각 독립적인 회로 소자가 구비되고, 패드의 위치가 대칭 구조로 이루어지는 것을 특징으로 하는 리드 온 칩 타입의 리드프레임.
KR1019960023268A 1996-06-24 1996-06-24 리드 온 칩 리드프레임 및 이를 이용한 반도체 소자 패키지 KR100224770B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019960023268A KR100224770B1 (ko) 1996-06-24 1996-06-24 리드 온 칩 리드프레임 및 이를 이용한 반도체 소자 패키지
TW086107041A TW384533B (en) 1996-06-24 1997-05-24 Lead-on-chip lead frame and semiconductor package using the same
US08/863,307 US5907186A (en) 1996-06-24 1997-05-27 Lead-on-clip lead frame and semiconductor package using the same
JP9155161A JP2866362B2 (ja) 1996-06-24 1997-06-12 リードオンチップリードフレーム及びこれを用いた半導体素子のパッケージ
CN97111828A CN1073283C (zh) 1996-06-24 1997-06-24 芯片上引线型引线框架

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960023268A KR100224770B1 (ko) 1996-06-24 1996-06-24 리드 온 칩 리드프레임 및 이를 이용한 반도체 소자 패키지

Publications (2)

Publication Number Publication Date
KR980006563A true KR980006563A (ko) 1998-03-30
KR100224770B1 KR100224770B1 (ko) 1999-10-15

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ID=19463073

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Application Number Title Priority Date Filing Date
KR1019960023268A KR100224770B1 (ko) 1996-06-24 1996-06-24 리드 온 칩 리드프레임 및 이를 이용한 반도체 소자 패키지

Country Status (5)

Country Link
US (1) US5907186A (ko)
JP (1) JP2866362B2 (ko)
KR (1) KR100224770B1 (ko)
CN (1) CN1073283C (ko)
TW (1) TW384533B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100427541B1 (ko) * 1997-06-30 2004-07-19 주식회사 하이닉스반도체 패턴 필름 제조 방법 및 이를 이용한 칩 모듈

Families Citing this family (9)

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US6268643B1 (en) * 1997-12-22 2001-07-31 Texas Instruments Incorporated Lead frame device for delivering electrical power to a semiconductor die
US6534861B1 (en) 1999-11-15 2003-03-18 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
KR100381892B1 (ko) * 1999-11-24 2003-04-26 삼성전자주식회사 듀얼-리드 타입 정방형 반도체 패키지 및 그를 사용한양면 실장형 메모리 모듈
US6445603B1 (en) 2000-08-21 2002-09-03 Micron Technology, Inc. Architecture, package orientation and assembly of memory devices
US6275446B1 (en) 2000-08-25 2001-08-14 Micron Technology, Inc. Clock generation circuits and methods
US6541849B1 (en) * 2000-08-25 2003-04-01 Micron Technology, Inc. Memory device power distribution
US8174099B2 (en) * 2008-08-13 2012-05-08 Atmel Corporation Leadless package with internally extended package leads
TW201530726A (zh) * 2014-01-29 2015-08-01 Eorex Corp 記憶體與記憶體儲存裝置
TWI539565B (zh) * 2014-01-29 2016-06-21 森富科技股份有限公司 記憶體與記憶體球位焊墊之佈局方法

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US5365113A (en) * 1987-06-30 1994-11-15 Hitachi, Ltd. Semiconductor device
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
JPH039407A (ja) * 1989-06-06 1991-01-17 Fujitsu Ten Ltd 制御装置の検査方式
JP2567961B2 (ja) * 1989-12-01 1996-12-25 株式会社日立製作所 半導体装置及びリ−ドフレ−ム
US5229329A (en) * 1991-02-28 1993-07-20 Texas Instruments, Incorporated Method of manufacturing insulated lead frame for integrated circuits
US5250840A (en) * 1992-02-24 1993-10-05 Samsung Electronics Co., Ltd. Semiconductor lead frame with a chip having bonding pads in a cross arrangement
SG44840A1 (en) * 1992-09-09 1997-12-19 Texas Instruments Inc Reduced capacitance lead frame for lead on chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100427541B1 (ko) * 1997-06-30 2004-07-19 주식회사 하이닉스반도체 패턴 필름 제조 방법 및 이를 이용한 칩 모듈

Also Published As

Publication number Publication date
CN1073283C (zh) 2001-10-17
KR100224770B1 (ko) 1999-10-15
JPH1056123A (ja) 1998-02-24
US5907186A (en) 1999-05-25
CN1170235A (zh) 1998-01-14
TW384533B (en) 2000-03-11
JP2866362B2 (ja) 1999-03-08

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