KR930011179A - LOC(Lead on Chip) 패케이지 - Google Patents

LOC(Lead on Chip) 패케이지 Download PDF

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Publication number
KR930011179A
KR930011179A KR1019910019552A KR910019552A KR930011179A KR 930011179 A KR930011179 A KR 930011179A KR 1019910019552 A KR1019910019552 A KR 1019910019552A KR 910019552 A KR910019552 A KR 910019552A KR 930011179 A KR930011179 A KR 930011179A
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KR
South Korea
Prior art keywords
lead
bonding
adhesive tape
package
pads
Prior art date
Application number
KR1019910019552A
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English (en)
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KR940006581B1 (ko
Inventor
공병식
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910019552A priority Critical patent/KR940006581B1/ko
Publication of KR930011179A publication Critical patent/KR930011179A/ko
Application granted granted Critical
Publication of KR940006581B1 publication Critical patent/KR940006581B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음

Description

LOC (Lead on Chip) 패케이지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a도는 일반적인 패케이지의 부분 절결사시도.
제1b도는 일반적인 패케이지에 이용되는 리드프레임의 부분사시도.
제2a도는 LOC 패케이지의 부분 절결사시도.
제2b도는 LOC 패케이지에 이용되는 리드프레임의 부분사시도.
제3a도는 본 발명에 의한 리드프레임 및 다이의 분리사시도.
제3b도는 제3a도를 결합시킨 상태의 평면도.
제4도는 제3a도의 리드프레임과 다이클 상호 부착한 상태에서 와이어 본딩을 실시한 상태를 도시한 부분절결사시도.
* 도면의 주요부분에 대한 부호의 설명
1,10 및20 : 리드프레임 2 : 패드
16A,16B 및 26 : 접착테이프 4,14 및 24 : 다이
4A,14A 및 24A : 본딩패드

Claims (2)

  1. 다수의 본딩패드가 형성된 다이와 리드프레임을 접착하여 각 본딩패드와 이에 대응하는 각 리드를 와이어로 접속시켜 성형처리한 I.C 패케이지에 있어서, 패드를 형성하지 않고 패드가 형성되는 공간을 향하여 각 리드(22) 선단에 각 리드(22)를 소정길이로 연장시킨 연장부(E)를 구성한 리드프레임(20)과, 상기 각 리드(22)의 연장부(E) 저면과 대응하여 상기 리드프레임(20) 저면에 부착되는 양면의 접착테이프(26)와, 중앙부는 상기 접착테이프(26)와의 대응면(A)으로, 외곽면에는 다수의 본딩패드(24A)를 각각 구성하되, 각 본딩패드(24A)는 상기 리드프레임(20)의 리드(22)와 이에 인접하는 또다른 리드(22)간에 형성되는 측면 공간부에 위치하도록 구성된 다이(24)로 이루어져 상기 접착테이프(26)의 한면을 상기 리드프레임(20)의 각리드 연장부(E) 저면에 부착하고, 상기 다이(24) 중앙부(A)를 상기 접착테이프(26)의 또다른 면에 부착시켜 상기 각 본드 패드(24A)가 상기 각 리드(22)간의 측면에 위치하여 각 리드연장부(E)와 대응 본딩패드(24A)간을 와이어 본딩시켜 구성한 것을 특징으로 하는 LOC 패케이지.
  2. 제1항에 있어서, 상기 각 본딩패드(24A)는 인접하는 또다른 본딩패드와, 상기 리드(22)간의 폭보다 넓은 간격을 유지하는 것을 특징으로 하는 LOC 패케이지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910019552A 1991-11-05 1991-11-05 LOC (Lead on Chip) 패케이지 KR940006581B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910019552A KR940006581B1 (ko) 1991-11-05 1991-11-05 LOC (Lead on Chip) 패케이지

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910019552A KR940006581B1 (ko) 1991-11-05 1991-11-05 LOC (Lead on Chip) 패케이지

Publications (2)

Publication Number Publication Date
KR930011179A true KR930011179A (ko) 1993-06-23
KR940006581B1 KR940006581B1 (ko) 1994-07-22

Family

ID=19322269

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910019552A KR940006581B1 (ko) 1991-11-05 1991-11-05 LOC (Lead on Chip) 패케이지

Country Status (1)

Country Link
KR (1) KR940006581B1 (ko)

Also Published As

Publication number Publication date
KR940006581B1 (ko) 1994-07-22

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