JPS55124248A - Leadless package - Google Patents

Leadless package

Info

Publication number
JPS55124248A
JPS55124248A JP3246279A JP3246279A JPS55124248A JP S55124248 A JPS55124248 A JP S55124248A JP 3246279 A JP3246279 A JP 3246279A JP 3246279 A JP3246279 A JP 3246279A JP S55124248 A JPS55124248 A JP S55124248A
Authority
JP
Japan
Prior art keywords
pads
layer
chip
package
miniaturize
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3246279A
Other languages
Japanese (ja)
Inventor
Masayasu Yonetsuka
Koji Soma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3246279A priority Critical patent/JPS55124248A/en
Publication of JPS55124248A publication Critical patent/JPS55124248A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Abstract

PURPOSE:To miniaturize a leadless package by forming IC chip wiring bonding pads stepwise in more than two rows and connecting them to back surface soldering pads aligned in more than two rows using both side conducting through holes. CONSTITUTION:Die attachement metallize 4 and wire bonding pads 5, 5'are stepwisely formed on the first, second and third layers 1, 2 and 3 of a package, soldering pads 6, 6' are formed corresponding to the respective bonding pads, and they are conducted via through holes. The fourth layer 9 for sealing cap is formed on the third layer. Wires are stereoscopically arrayed via fine wires 8 between an IC chip 7 and the pads 5, 5', and the pads 6, 6' are effectively wired on the back surface of the layer 1. Accordingly, even if the number of the pads of the IC chip is increased, it can miniaturize the package area.
JP3246279A 1979-03-20 1979-03-20 Leadless package Pending JPS55124248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3246279A JPS55124248A (en) 1979-03-20 1979-03-20 Leadless package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3246279A JPS55124248A (en) 1979-03-20 1979-03-20 Leadless package

Publications (1)

Publication Number Publication Date
JPS55124248A true JPS55124248A (en) 1980-09-25

Family

ID=12359627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3246279A Pending JPS55124248A (en) 1979-03-20 1979-03-20 Leadless package

Country Status (1)

Country Link
JP (1) JPS55124248A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860562A (en) * 1981-09-14 1983-04-11 テキサス・インスツルメンツ・インコ−ポレイテツド Package for high terminal number integrated circuit device
US4638348A (en) * 1982-08-10 1987-01-20 Brown David F Semiconductor chip carrier
JPS62123744A (en) * 1985-11-22 1987-06-05 Nec Corp Semiconductor device
JPS62229861A (en) * 1986-01-21 1987-10-08 ユニシス・コ−ポレ−シヨン Manufacture of integrated circuit package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123271A (en) * 1973-03-28 1974-11-26
JPS5111168A (en) * 1974-07-19 1976-01-29 Hitachi Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123271A (en) * 1973-03-28 1974-11-26
JPS5111168A (en) * 1974-07-19 1976-01-29 Hitachi Ltd

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860562A (en) * 1981-09-14 1983-04-11 テキサス・インスツルメンツ・インコ−ポレイテツド Package for high terminal number integrated circuit device
US4638348A (en) * 1982-08-10 1987-01-20 Brown David F Semiconductor chip carrier
JPS62123744A (en) * 1985-11-22 1987-06-05 Nec Corp Semiconductor device
JPS62229861A (en) * 1986-01-21 1987-10-08 ユニシス・コ−ポレ−シヨン Manufacture of integrated circuit package

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