KR970702582A - 반도체 집적회로장치 및 그 제조방법과 제조장치(semiconductor integrated circuit device, and method and apparatus for manufacturingit) - Google Patents

반도체 집적회로장치 및 그 제조방법과 제조장치(semiconductor integrated circuit device, and method and apparatus for manufacturingit)

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Publication number
KR970702582A
KR970702582A KR1019960705924A KR19960705924A KR970702582A KR 970702582 A KR970702582 A KR 970702582A KR 1019960705924 A KR1019960705924 A KR 1019960705924A KR 19960705924 A KR19960705924 A KR 19960705924A KR 970702582 A KR970702582 A KR 970702582A
Authority
KR
South Korea
Prior art keywords
lead
integrated circuit
circuit device
semiconductor integrated
semiconductor
Prior art date
Application number
KR1019960705924A
Other languages
English (en)
Inventor
히로타카 니시자와
도모요시 미우라
이치로오 안죠오
마사미치 이시하라
마사히로 야마무라
사다오 모리타
다카시 아라키
기요시 이노우에
도시오 스가노
데츠지 고하라
도시오 야마다
야스시 세키네
요시아키 아나타
마사카츠 고토오
노리히코 가사이
시노부 다케우라
무츠오 츠쿠다
야스노리 야마구치
지로오 사와다
히데토시 이와이
세이이치로오 츠쿠이
다다오 가지
노보루 시오자와
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
스즈키 진이치로
히타치 쬬오 엘.에스.아이.엔지니어링 가부시키가이샤
야마모토 마사유키
히타치 도오부 세미콘덕터 가부시키가이샤
스즈키 시게루
히타치 훗카이 세미콘덕터 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼, 스즈키 진이치로, 히타치 쬬오 엘.에스.아이.엔지니어링 가부시키가이샤, 야마모토 마사유키, 히타치 도오부 세미콘덕터 가부시키가이샤, 스즈키 시게루, 히타치 훗카이 세미콘덕터 가부시키가이샤 filed Critical 가나이 쓰토무
Publication of KR970702582A publication Critical patent/KR970702582A/ko

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Abstract

반도체칩을 탑재한 리드프레임의 소정수를 적층하여 일괄 봉지한 수지패키지(2A)를 머더 소켓(3A)에 탑재하고, 수지패키지(2A)의 측면으로부티 인출된 리드프레임의 리드(6)와 그 리드(6)의 연장방향과 교차하는 방향으로 연장하는 머더 소켓(3A)의 모듈리드(9)를 전기적으로 접속한, 초소형 대용량의 DRAM 모듈이다.

Description

반도체 집적회로장치 및 그 제조방법과 제조장치(SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD AND APPARATUS FOR MANUFACTURING)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일 실시예인 DRAM 모듈의 전방사시도.

Claims (52)

  1. 반도체칩을 탑재한 리드프레임의 소정수를 적층하여 일괄 봉지한 수지패키지를 머더 소켓에 탑재하고, 상기 수지패키지로부터 인출한 상기 리드프레임의 리드와, 상기 리드의 연장하는 방향과 교차하는 방향으로 연장하는 상기 머더 소켓의 모듈리드를 전기적으로 접속한 것을 특징으로 하는 반도체 집적회로장치.
  2. 제1항에 있어서, 상기 반도체칩에 대응한 리드 중, 공통 접속되는 리드는 동일패턴에 의해 형성되어 상기 모듈리드에 접속되며, 독립하여 외부로 유도되는 각 층의 리드는 적층방향에 있어서 분리 배치되어 상기 모듈리드에 접속되는 것을 특징으로 하는 반도체 집적회로장치.
  3. 제2항에 있어서, 상기 반도체칩은 반도체메모리를 구성하는 것이며, 상기 공통접속되는 리드는 어드레스신호 및 제어신호용의 리드이고, 상기 독립하여 외부로 유도되는 리드는 데이터입출력신호용 리드인 것을 특징으로 하는 반도체 집적회로장치.
  4. 제2항에 있어서, 상기 반도체칩은 데이터입출력용의 비트수에 대해 적어도 +1개로 이루어지고, 상기 머더 소켓에는 1개의 모듈리드에 대해 2개의 반도체칩의 입출력신호용 리드에 접속가능하게 된 배선패턴이 링모양으로 형성되고, 상기 반도체칩 중의 l개에 불량이 발생한 때에는, 상기 불량의 반도체칩에 대응한 입출력신호용 리드를 제외하고 상기 머더 소켓의 모듈리드와 각 반도체칩의 입출력 신호용 리드를 접속하는 것을 특징으로 하는 반도체 집적회로장치.
  5. 제4항에 있어서, 상기 반도체칩은 N+1개로 이루어지고, 모든 반도체칩이 양품인 때에는 1비트를 패리티비트로 쓰도록 상기 리드와 상기 모듈리드를 접속하여 패리티 비트부(付) 메모리로 사용하고, 1개의 반도체칩에 불량이 발생한 때에는, 상기 불량의 반도체칩에 대응한 입출력신호용 리드를 써서 상기 리드와 상기 모듈리드를 접속함으로써 N비트의 메모리로서 사용하는 것을 특징으로 하는 반도체 집적회로장치.
  6. 제2항에 있어서, 상기 반도체칩은 데이터입출력용의 비트수 N에 대하여 N+1개로 이루어지며, 그 중 N개는 메모리칩이고, 나머지 1개의 반도체칩은 상기 N개의 메모리칩에 있어서 발생판 결합비트를 구제하기 이한 결합구제칩인 것을 특징으로 하는 반도체 집적회로장치.
  7. 제6항에 있어서, 상기 N개의 메모리칩은 그 조립 전의 시점에서 상기 결함구체칩에 의해 구제가 가능한 결함을 갖는 것을 특징으로 하는 반도체 집적회로장치.
  8. 제6항에 있어서, 상기 N개의 메모리칩은 DRAM칩인 것을 특징으로 하는 반도체 집적회로장치.
  9. 제1항에 있어서, 상기 각 리드프레임은, 이들을 하나의 세트 리드프레임으로 하여 동일공정에서 일괄 페터닝된 것을 특징으로 하는 반도체 집적회로장치.
  10. 제1항에 있어서, 상기 각 리드프레임은, 모울드 라인상에 절연테이프를 접합한 테이프 댐방식의 리드프레임인 것을 특징으로 하는 반도체 집적회로장치.
  11. 제1항에 있어서, 상기 각 리드프레임의 각각의 동일위치에 한쌍의 모울드용 게이트구멍을 마련한 것을 특징으로 하는 반도체 집적회로장치.
  12. 제1항에 있어서, 상기 각 리드프레임의 각각의 일부에, 리드프레임마다 다른 패턴의 인덱스구멍을 마련한 것을 특징으로 하는 반도체 집적회로장치.
  13. 제1항에 있어서, 상기 각 리드프레임의 각각의 일부에 그 각부를 분리하기 위한 하프에칭라인을 마련한 것을 특징으로 하는 반도체 집적회로장치.
  14. 제1항에 있어서, 상기 각 리드프레임의 전원공급용 리드에 전원임피던스를 줄이기 위한 디커플링 콘덴서를 탑재한 것을 특징으로 하는 반도체 집적회로장치.
  15. 제1항에 있어서, 상기 수지패키지로부터 인출된 상기 리드프레임의 리드는, 상기 수지패키지로부터 연장되는 길이가 적층방향의 열변형을 균형잡도록 하는 최적길이를 갖는 판 용수철 구조로 구성되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  16. 제1항에 있어서, 상기 수지패키지의 내부에 더미의 리드프레임을 봉지한 것을 특징으로 하는 반도체 집적회로장치.
  17. 제1항에 있어서, 상기 반도체칩은 리드·온·칩방식에 의해서 상기 리드프레임에 탑재되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  18. 제1항에 있어서, 상기 리드프레임에 탑재된 상기 반도체칩은, 그 중심이 상기 수지패키지의 중심보다도, 상기 리드프레임의 데이터입출력신호용 리드측에 배치되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  19. 제18항에 있어서, 상기 데이터입출력신호용 리드와 반대측의 리드프레임에 더미의 반도체칩을 탑재한 것을 특징으로 하는 반도체 집적회로장치.
  20. 제18항에 있어서, 상기 데이터입출력신호용 리드와 반대측 리드프레임의 진원공급용 리드에 전원임피던스를 줄이기 위한 디커플링 콘덴서를 탑재한 것을 특징으로 하는 반도체 집적회로장치.
  21. 제18항에 있어서, 상기 데이터입출력신호용 리드와 반대측 리드프레임의 전원공급용 리드에 전원임피던스를 줄이기 위한 디커플링 콘덴서를 형성한 더미의 반도체칩을 탑재한 것을 특징으로 하는 반도체 집적회로장치.
  22. 제1항에 있어서, 상기 리드프레임을 리드패턴이 각각 같은 복수 세트의 리드프레임으로 구성하고, 각각의 세트의 리드프레임을 수평면 내에서 서로 180도 반전하여 배치한 젓을 특징으로 하는 반도체 집적회로장치.
  23. 제4항에 있어서, 상기 배선패턴은, 2개의 반도체칩의 입출력신호용 리드에 접속가능하게 된 링모양의 배선패턴이고, 상기 배선패턴의 접속은 땜납에 의해 행해지는 것을 특징으로 하는 반도체 집적회로장치.
  24. 제4항에 있어서, 상기 배선패턴은, 각 반도체칩의 입출력신호용 리드가 링모양으로 형성되고, 상기 배선패턴 사이가 적당히 에너지빔의 조사에 의해서 선택적으로 절단되어 1개의 입출력신호용 리드가 1개의 모듈리드에만 접속되는 것을 특징으로 하는 반도체 집적회로장치.
  25. 제1항에 있어서, 상기 머더 소켓의 모듈 리드를, 상기 수지패키지의 열팽창계수와 대략 같은 열팽창계수의 도전재료로 구성한 것을 특징으로 하는 반도체 집적회로장치.
  26. 제1항에 있어서, 상기 머더 소켓의 모듈 리드를, 상기 머더 소켓의 대향하는 2변을 따라 2열씩 배치한 것을 특징으로 하는 반도체 집적회로장치.
  27. 제1항에 있어서, 상기 머더 소켓의 내부에, 상기 수지패키지의 모듈기능을 확장 또는 변경하기 위한 기능을 구비한 반도체칩을 탑재한 것을 특징으로하는 반도체 집적회로장치.
  28. 제1항에 있어서, 상기 머더 소켓이 핀 그리드 어레이(PGA) 기판인 것을 특징으로 하는 반도체 집적회로장치.
  29. 제1항에 있어서, 상기 머더 소켓이 볼 그리드 어레이 기판인 것을 특징으로하는 반도체 집적회로장치.
  30. 반도체칩을 탑재한 리드프레임의 소정수를 적층하여 일괄 봉지한 수지패키지로부터 인출한 상기 리드프레임의 리드와, 상기 리드의 연장하는 방향과 교차하는 방향으로 연장하는 모듈리드를 전기적으로 접속하여, 상기 모듈리드의 하단부를 프린트 배선기판에 실장가능하도록 성형한 것을 특징으로 하는 반도체 집적회로장치.
  31. 제30항에 있어서, 상기 수지패키지에는 4개 또는 그 이상의 반도체칩이 봉지되고, 상기 수지패키지와 상기 모듈리드의 각각의 치수가 300mi1-SOJ의 EIAJ 규격의 범위내에 있는 것을 특징으로 하는 반도체 집적회로장치.
  32. 제30항에 있어서, 상기 모듈리드를 단면이 원형인 와이어로 구성한 것을 특징으로 하는 반도체 집적회로장치.
  33. 제30항에 있어서, 상기 모듈리드의 하단부를 J벤드형으로 한 것을 특징으로 하는 반도체 집적회로장치.
  34. 제30항에 있어서, 상기 모듈리드의 하단부를 플랫리드로 한 것을 특징으로 하는 반도체 집적회로장치.
  35. 제30항에 있어서, 상기 모듈리드와 상기 리드는, 어느 쪽인가의 한쪽에 마련한 트인구멍 내에 다른쪽을 삽입함으로써 접속되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  36. 제30항에 있어서, 상기 모듈리드와 상기 리드는, 어느 쪽인가의 한쪽에 마련한 홈 내에 다른쪽을 압입함으로써 접속되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  37. 제30항에 있어서, 상기 모듈리드와 상기 리드는, 각각의 표면에 도금한 땜납을 용융시키는 것에 의해 접속되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  38. 제35항에 있어서, 상기 리드의 일부분의 지름을 다른 부분보다도 굵게 한 것을 특징으로 하는 반도체 집적회로장치.
  39. 반도체칩을 탑재한 리드프레임의 소정수를 적층하여 일괄 봉지한 수지패키지로부터 인출한 상기 리드프레임의 리드와, 상기 리드의 연장하는 방향과 교차하는 방향으로 연장하는 모듈리드를 전기적으로 접속하고, 상기 리드 중, 최하층 리드의 하단부를 프린트 배선기판에 실장가능하도록 성형한 것을 특징으로 하는 반도체 집적회로장치.
  40. 상금형과, 하금형과, 각 층 간에 대응하여 마련되고, 적층방향에 대하여 수평인 방향으로 이동가능하게 되고, 리드프레임의 두께, 상기 리드프레임에 반도제칩을 접속하는 절연테이프의 두께, 본딩와이어의 루프높이 및 층간의 수지층의 두께에 대응한 높이를 가지는 가동금형을 사용하여, 하금형, 제1층째 리드프레임, 제1층째의 가동금형, 제2층째의 리드프레임, 제2층째의 가동금형의 순서로 이들을 세로로 쌓고, 최상층 리드프레임의 상부에 상금형을 배치하는 제1공정과, 상기 상금형 또는 하금형에 마련된 게이트구멍으로부터 수지를 주입하는 제2공정과, 상기 수지가 경화한 후에, 상기 리드프레임의 불필요 부분을 절단하여 제거함과 더불어, 상기 상금형 또는 하금형은 상대적으로 적층방향으로 이동시키고, 상기 가동금형은 상대적으로 수평방향으로 이동시켜 분리함으로써, 수지패키지를 형성하는 제3공정과, 상기 수지패키지로부터 인출된 상기 리드프레임의 리드와, 상기 리드의 연장하는 방향과 교차하는 방향으로 연장하는 머더 소켓의 모듈리드를 전기적으로 접속함과 더불어, 상기 수지패키지를 상기 머더 소켓에 탑재하는 제4공정을 포함하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  41. 제40항에 있어서, 상기 반도체칩은 반도체 메모리를 구성하는 것이며, 상기 제4공정에 있어서 어드레스신호 및 제어신호용의 리드가 상기 머더 소켓의 공통의 모듈리드에 접속됨과 더불어, 데이터입출력신호용의 리드가 상기 머더 소켓의 독립한 모듈리드에 접속되고, 상기 제4공정 후에 상기 반도체 메모리의 초기 불량을 선별하기 위한 에이징 또는 번인처리를 한 결과에 대응해서, 1개의 모듈리드에 대해 2개의 반도체칩의 입출력신호용 리드로 접속가능하게 된 배선패턴이 링모양으로 형성되게 되는 리던던시 계층셀렉터의 선택적인 접속을 하는 공정을 포함하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  42. 제40항에 있어서, 상기 반도체칩은 반도체 메모리를 구성하는 것이며, 상기 제3공정 후에 상기 반도체 메모리의 초기불량을 선별하기 위한 에이징 또는 번인처리가 행해지고, 그 결과에 대응해서 상기 머더 소켓에 형성된 링모양의 배선패턴이 에너지빔의 조사에 의해 선택적으로 절단되는 공정을 포함하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  43. 상금형과, 하금형과, 각 층간에 대응하여 마련되고, 적층방향에 대하여 수평인 방향으로 이동가능하게 되고, 리드프레임의 두께, 상기 리드프레임에 반도체 칩을 접속하는 절연테이프의 두께, 본딩와이어의 루프높이 및 층간의 수지층의 두께에 대응한 높이를 가지는 가동금형을 구비한 것을 특징으로 하는 반도체 집적회로장치의 제조장치.
  44. 제43항에 있어서, 적층방향에 대하여 수평인 방향으로 2분할되는 상기 가동금형과 한쪽과 다른쪽을 서로 비대칭형상으로 한 것을 특징으로 하는 반도체 집적회로장치의 제조장치.
  45. 제43항에 있어서, 상기 가동금형을 수지 또는 수지가 함침된 종이로 구성한 것을 특징으로 하는 반도체 집적회로장치의 제조장치.
  46. 제43항에 있어서, 상기 상금형, 하금형 및 가동금형으로 구성되는 캐버티를 적층방향에 복수배치하고, 최상층 캐버티의 위쪽에 마련한 게이트구멍을 통하여 상기 각각의 캐버티에 수지를 주입하도록 구성한 것을 특징으로 하는 반도체 집적회로장치의 제조장치.
  47. 사이가 서로 떨어진 상태로 적층된 복수의 리드프레임을 일괄하여 수지봉지한 수지봉지형의 반도체 집적회로장치에 있어서, 수지봉지체의 적층방향의 두께가 3.759mm 이하의 박형(薄型)인 것을 특징으로 하는 반도체 집적회로장치.
  48. 제47항에 있어서, 상기 수지봉지체의 외부로 인출된 다른 층을 이루는 리드 간을 접속하는 접속도체를 구비한 것을 특징으로 하는 반도체 집적회로장치.
  49. 제47항에 있어서, 상기 수지봉지형의 반도체 집적회로장치는, DRAM인 것을 특징으로 하는 반도체 집적회로장치.
  50. 제48항에 있어서, 상기 수지봉지형의 반도체 집적회로장치는, DRAM인 것을 특징으로 하는 반도체 집적회로장치.
  51. 사이가 서로 떨어진 상태로 적층된 복수 리드프레임을 일괄하여 수지봉지한 것을 특징으로 하는 반도체 집적회로장치.
  52. 복수의 리드프레임을 사이가 서로 떨어진 상태로 적층하고, 그들을 일괄하여 수지봉지하는 반도체 집적회로장치의 제조방법에 있어서, 리드프레임마다에 수지주입부를 마련하고, 수지봉지 캐버티의 일측면으로부터 봉지수지를 주입하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960705924A 1994-04-16 1995-04-05 반도체 집적회로장치 및 그 제조방법과 제조장치(semiconductor integrated circuit device, and method and apparatus for manufacturingit) KR970702582A (ko)

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US6054764A (en) * 1996-12-20 2000-04-25 Texas Instruments Incorporated Integrated circuit with tightly coupled passive components
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