CN100521182C - 具有高密度引脚排列的导线架封装结构 - Google Patents

具有高密度引脚排列的导线架封装结构 Download PDF

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CN100521182C
CN100521182C CN 200610074683 CN200610074683A CN100521182C CN 100521182 C CN100521182 C CN 100521182C CN 200610074683 CN200610074683 CN 200610074683 CN 200610074683 A CN200610074683 A CN 200610074683A CN 100521182 C CN100521182 C CN 100521182C
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lead frame
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kenel
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CN101055860A (zh
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洪志斌
欧英德
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Advanced Semiconductor Engineering Inc
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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Abstract

本发明提供一种具有高密度引脚排列的导线架封装(lead frame basepackage)结构。上述导线架封装结构包含有一芯片、若干个第一型态引脚与若干个第二型态引脚，其中第一型态引脚与第二型态引脚位于芯片的至少一侧，并与芯片电性连接。第一型态引脚与第二型态引脚选自J型引脚、L型引脚与I型引脚中的任二种，且第一型态引脚的焊接端与第二型态引脚的焊接端呈错位方式排列，使引脚可以呈高密度排列而不发生短路。

Description

具有高密度引脚排列的导线架封装结构
【技术领域】
本发明关于一种导线架封装(lead frame base package)结构，尤其是关于一种通过引脚焊接端的错位排列以使引脚可以呈高密度排列的导线架封装结构。
【背景技术】
由于具有低制造成本以及高可靠性的优势，在集成电路封装领域中导线架封装构造已被使用很长一段时间，尤其对于低引脚数芯片具有相当的市场。
请参考图1、图2及图3，图1为现有的导线架封装构造10的俯视图、图2为现有的导线架封装构造10的侧视图，而图3为现有的印刷电路板30的俯视图。如图1及图2所示，现有导线架封装构造10包含有一芯片12、若干个引脚14与一置晶区16，其中芯片12上有若干个接合垫片18且各引脚14分别包含一内焊接端22与一外焊接端24，而接合垫片18则电性连接至引脚14的内焊接端22。另外，有一封装胶体26包覆芯片12与内焊接端22并固化成型，在此假设此封装胶体26为透明材质以方便检视封装胶体26内部的构造。如图3所示，引脚14的外焊接端24电性连接至印刷电路板30上的对应连接端32。尤其注意的是，现有导线架封装构造10中，各个内焊接端22之间、各个外焊接端24之间与各个对应的连接端32之间皆为单列排列，其中，各外焊接端24之间有一间距(lead pitch)24a，而各连接端32之间有一间距32a。
然而，随着集成电路产品不断地精密化的需求，为了减少封装构造的尺寸且同时不减少引脚数，或者增加引脚数且同时不增加封装构造的尺寸，就必须发展出高密度引脚排列的导线架结构。现有的导线架封装构造10成为精密化的一项限制，因为欲增加引脚14的密度就需要缩小相邻引脚14之间的间距24a，而增加串讯(cross-talk)或讯号干扰的机率并且造成封装构造制造上的困难。理论上，一引脚14应该仅电连接至该引脚14对应的连接端32，但由于受热膨胀、焊接材料的流动或对位偏移(misalignment)等因素，会导致导电材料导通引脚14与引脚14之间，因此产生电性短路的情形，而影响产品的正常操作。
在现有导线架封装构造10中，若想要缩小导线架封装的尺寸或是在不增加尺寸的情况下增加引脚14的数目，都必须增加引脚14的密度且增加引脚14的内焊接端22及外焊接端24的密度。焊接端22、24的密度增加时，焊接端22、24之间的间距24a会缩小而造成串讯或讯号干扰的机率升高。因此本发明提出一种高密度引脚排列的导线架封装结构，以解决现有方法所存在的不足。
【发明内容】
本发明的主要目的在于提供一种具有高密度引脚排列的导线架结构，以解决现有技术无法克服的难题。
本发明导线架封装结构包含有：一芯片；若干个第一型态引脚位于该芯片之至少一侧，并与该芯片电性连接；以及若干个第二型态引脚位于该芯片之至少一侧，并与该芯片电性连接，其中该些第一型态引脚与该些第二型态引脚选自J型引脚、L型引脚与I型引脚中的任二种。
由于第一型态引脚与第二型态引脚选自J型引脚、L型引脚与I型引脚中的任二种，使得第一型态引脚的焊接端与第二型态引脚的焊接端可以不位于同一单排上而呈错位方式排列。因此，在相邻引脚距离不变的情形下，焊接端与焊接端之间距离将会增加，而在焊接端彼此之间距离不变的情形下，相邻引脚距离将可以缩小。由于引脚排列密度的提高，可以缩小导线架封装结构的尺寸或者是增加导线架封装结构的焊接端的数目，使得精密度提高。
【附图说明】
图1为现有导线架封装构造的俯视图。
图2为现有导线架封装构造的侧视图。
图3为现有印刷电路板的俯视图。
图4为本发明第一较佳实施例的导线架封装构造的俯视图。
图5为本发明第一较佳实施例的导线架封装构造的侧视图。
图6为本发明第一较佳实施例的印刷电路板的俯视图。
图7为本发明第二较佳实施例的导线架封装构造的俯视图。
图8为本发明第二较佳实施例的导线架封装构造的侧视图。
图9为本发明第二较佳实施例的印刷电路板的俯视图。
图10为本发明第三较佳实施例的导线架封装构造的俯视图。
图11为本发明第三较佳实施例的导线架封装构造的侧视图。
图12为本发明第三较佳实施例的印刷电路板的俯视图。
图13为本发明第四较佳实施例的导线架封装构造的俯视图。
图14为本发明第四较佳实施例的导线架封装构造的侧视图。
图15为本发明第四较佳实施例的印刷电路板的俯视图。
图16为引线键合封装的结构示意图。
图17为倒装接合封装的结构示意图。
【具体实施方式】
请参考图4至图6，图4为本发明第一较佳实施例的导线架封装构造40的俯视图，第5图为本发明第一较佳实施例的导线架封装构造40的侧视图，而图6为本发明第一较佳实施例的印刷电路板50的俯视图。如图4及图5所示，导线架封装结构40包含有一芯片封装42、若干个J型引脚44与若干个L型引脚46，其中各引脚44与46分别包含一内焊接端(未图示)与一外焊接端48，其中同一列的各外焊接端48之间有一间距48a。如图6所示，提供一印刷电路板50，其中印刷电路板50上具有若干个对应应于外焊接端的连接端52，而各连接端52之间有一间距52a。然后，在连接端52以外的印刷电路板50表面形成一防焊阻剂54以减低电路短路的可能性，而连接端52则藉由防焊阻剂开口(solderresist opening)曝露出。接着将引脚44与46的外焊接端48电性连接至印刷电路板50上的对应连接端52。本实施例的特点在于，各个外焊接端48彼此之间与各个对应的连接端52彼此之间皆为双列错位排列，而各个内焊接端(未图示)彼此之间为单列排列。除此之外，各个内焊接端之间不单局限于单列排列，亦可为双列错位排列。
若将引脚44与46结构与图1所示的现有的导线架封装结构10相比，在引脚间距相同的情况下，此实施例中的焊接端间距48a较现有结构的焊接端间距24a更大。在双列错位排列中，同一列焊接端的间距48a或同一列连接端的间距52a是单列排列时的二倍宽。另一方面，若在引脚间距相同的情况下，本发明的导线架封装结构可以比现有的导线架封装结构装设更多的连接端。
请参考图7至图9，图7为本发明第二较佳实施例的导线架封装构造60的俯视图，图8为本发明第二较佳实施例的导线架封装构造60的侧视图，而图9为本发明第二较佳实施例的印刷电路板70的俯视图。如图7及图8所示，与前述实施例不同之处在于，导线架封装结构60包含有一芯片封装62、若干个J型引脚64与若干个I型引脚66，其中各引脚64与66分别包含一内焊接端(未图示)与一外焊接端68。如图9所示，提供一印刷电路板70，其中印刷电路板70上具有若干个对应于外焊接端68的连接端72且在连接端72以外的印刷电路板70表面形成一防焊阻剂74。接着将引脚66与64的外焊接端68电性连接至印刷电路板70上的对应连接端72。
请参考图10至图12，图10为本发明第三较佳实施例的导线架封装构造80的俯视图，图11为本发明第三较佳实施例的导线架封装构造80的侧视图，而图12为本发明第三较佳实施例的印刷电路板90的俯视图。如图10及11所示，与前述二实施例不同之处在于，导线架封装结构80包含有一芯片封装82、若干个I型引脚84与若干个L型引脚86，其中各引脚84与86分别包含一内焊接端(未图示)与一外焊接端88。如图12所示，提供一印刷电路板90，其中印刷电路板90上具有若干个对应于外焊接端88的连接端92且在连接端92以外的印刷电路板90表面形成一防焊阻剂94。接着将引脚86与84的外焊接端88电性连接至印刷电路板90上的对应连接端92。
请参考图13至15，图13为本发明第四较佳实施例的导线架封装构造100的俯视图，图14为本发明第四较佳实施例的导线架封装构造100的侧视图，而图15为本发明第四较佳实施例的印刷电路板120的俯视图。如图13及14所示，与前述三实施例不同之处在于，导线架封装结构100包含有一芯片封装102、若干个J型引脚104、若干个I型引脚106与若干个L型引脚108，其中各引脚104、106与108分别包含一内焊接端(未图示)与一外焊接端112。如图15所示，提供一印刷电路板120，其中印刷电路板120上具有若干个对应于外焊接端112的连接端122，且在连接端122以外的印刷电路板120表面形成一防焊阻剂124。接着将引脚104、106与108的外焊接端112电性连接至印刷电路板120上的对应应连接端122。本实施例的特点在于，各个外焊接端112彼此之间与各个对应应的连接端122彼此之间皆为三列错位排列，使得同一列焊接端112之间或连接端122之间的间距更宽。
上述第一实施例至第四实施例的芯片与引脚接合方式可采用引线键合或倒装接合。请参考图16与17，图16为引线键合封装160的结构示意图，而图17为倒装接合封装170的结构示意图。如图16所示，利用接线162将芯片164与内焊接端166电性连接。如图17所示，利用锡球172将芯片174与内焊接端176电性连接。
在现有导线架封装构造中，增加引脚的密度就会增加引脚的焊接端的密度，且增加印刷电路板上对应的连接端的密度，使得电路短路或讯号干扰的可能性升高。由于本发明的焊接端采用错位排列，在与现有导线架封装结构拥有相同引脚密度的情况下，本发明的焊接端间距比现有方法的焊接端间距来得大，因此可减少短路或讯号干扰的机率。综上所述，本发明导线架封装结构可以提高焊接端或连接端的密度而不会影响到表面黏着技术的工艺(surface mount technology)或印刷电路板的运作。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (8)

1.一种导线架封装结构，包含一芯片；位于芯片至少一侧并与芯片电性连接的若干个第一型态引脚；以及位于芯片至少一侧并与芯片电性连接的若干个第二型态引脚；其特征在于：该些第一型态引脚与该些第二型态引脚选自J型引脚、L型引脚与I型引脚中的任二种，所述任二种不同型态的引脚由同一导线架形成，且所有引脚是由封装构造位于同一水平的表面向外延伸而成。
2.如权利要求1所述的导线架封装结构，其特征在于：所述第一型态引脚分别包含一第一内焊接端，所述第二型态引脚分别包含一第二内焊接端，用以与芯片电性连接。
3.如权利要求2所述的导线架封装结构，其特征在于：所述芯片利用引线键合方式分别与该些第一内焊接端以及该些第二内焊接端电性连接。
4.如权利要求2所述的导线架封装结构，其特征在于：所述芯片利用倒装方式直接与该些第一内焊接端以及该些第二内焊接端电性连接。
5.如权利要求4所述的导线架封装结构，其特征在于：该些第一内焊接端与芯片中央的距离，以及该些第二内焊接端与芯片中央的距离不同，藉此该些第一内焊接端与该些第二内焊接端呈错位方式排列。
6.如权利要求1所述的导线架封装结构，其特征在于：该些第一型态引脚与该些第二型态引脚为交错排列。
7.如权利要求1所述的导线架封装结构，其特征在于：该些第一型态引脚分别包含有一第一外焊接端，该些第二型态引脚分别包含有一第二外焊接端。
8.如权利要求7所述的导线架封装结构，其特征在于：该些第一外焊接端与该芯片中央的距离，以及该些第二外焊接端与芯片中央的距离不同，藉此该些第一外焊接端与该些第二外焊接端呈错位方式排列。
CN 200610074683 2006-04-11 2006-04-11 具有高密度引脚排列的导线架封装结构 Expired - Fee Related CN100521182C (zh)

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