CN101370352B - 一种印刷电路板及其制作方法和球栅阵列焊盘图案 - Google Patents
一种印刷电路板及其制作方法和球栅阵列焊盘图案 Download PDFInfo
- Publication number
- CN101370352B CN101370352B CN2008101310457A CN200810131045A CN101370352B CN 101370352 B CN101370352 B CN 101370352B CN 2008101310457 A CN2008101310457 A CN 2008101310457A CN 200810131045 A CN200810131045 A CN 200810131045A CN 101370352 B CN101370352 B CN 101370352B
- Authority
- CN
- China
- Prior art keywords
- pad
- array
- width
- adjacent
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/837,835 US7906835B2 (en) | 2007-08-13 | 2007-08-13 | Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package |
US11/837,835 | 2007-08-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101370352A CN101370352A (zh) | 2009-02-18 |
CN101370352B true CN101370352B (zh) | 2012-02-08 |
Family
ID=40070838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008101310457A Expired - Fee Related CN101370352B (zh) | 2007-08-13 | 2008-08-13 | 一种印刷电路板及其制作方法和球栅阵列焊盘图案 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7906835B2 (zh) |
EP (1) | EP2026641A3 (zh) |
KR (1) | KR20090017447A (zh) |
CN (1) | CN101370352B (zh) |
HK (1) | HK1129524A1 (zh) |
TW (1) | TWI399146B (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101846601B (zh) * | 2010-03-31 | 2011-08-31 | 伟创力电子科技(上海)有限公司 | 球栅阵列封装切片试块的制作方法 |
JP5710152B2 (ja) * | 2010-04-15 | 2015-04-30 | 日本メクトロン株式会社 | 多層フレキシブルプリント配線板の製造方法 |
CN201789682U (zh) * | 2010-07-23 | 2011-04-06 | 中兴通讯股份有限公司 | 四层通孔印刷电路板及应用该印刷电路板的移动终端 |
US20120267779A1 (en) | 2011-04-25 | 2012-10-25 | Mediatek Inc. | Semiconductor package |
US8664541B2 (en) | 2011-07-25 | 2014-03-04 | International Business Machines Corporation | Modified 0402 footprint for a printed circuit board (‘PCB’) |
CN102928279B (zh) * | 2012-11-13 | 2015-07-08 | 无锡江南计算技术研究所 | 金相灌样二次填胶方法 |
US9560771B2 (en) * | 2012-11-27 | 2017-01-31 | Omnivision Technologies, Inc. | Ball grid array and land grid array having modified footprint |
KR102079795B1 (ko) | 2013-07-19 | 2020-02-21 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | 화상형성장치 및 칩 |
US9633965B2 (en) * | 2014-08-08 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method of the same |
US10043774B2 (en) * | 2015-02-13 | 2018-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit packaging substrate, semiconductor package, and manufacturing method |
US20170012081A1 (en) * | 2015-07-06 | 2017-01-12 | Xintec Inc. | Chip package and manufacturing method thereof |
JP6750872B2 (ja) | 2016-09-01 | 2020-09-02 | キヤノン株式会社 | プリント配線板、プリント回路板及び電子機器 |
CN106658940A (zh) * | 2016-10-31 | 2017-05-10 | 努比亚技术有限公司 | 一种球栅阵列印制电路板 |
JP7078821B2 (ja) * | 2017-04-28 | 2022-06-01 | 東北マイクロテック株式会社 | 固体撮像装置 |
US10818624B2 (en) * | 2017-10-24 | 2020-10-27 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for manufacturing the same |
CN108990265A (zh) * | 2018-08-28 | 2018-12-11 | 竞华电子(深圳)有限公司 | 一种可焊性pcb板及其制作工艺 |
CN212064501U (zh) * | 2020-03-13 | 2020-12-01 | 华为技术有限公司 | 电路板结构和电子设备 |
KR20230111542A (ko) * | 2022-01-18 | 2023-07-25 | 엘지이노텍 주식회사 | 반도체 패키지 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872051A (en) * | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
JPH1126919A (ja) * | 1997-06-30 | 1999-01-29 | Fuji Photo Film Co Ltd | プリント配線板 |
US6268568B1 (en) * | 1999-05-04 | 2001-07-31 | Anam Semiconductor, Inc. | Printed circuit board with oval solder ball lands for BGA semiconductor packages |
US7433201B2 (en) * | 2000-09-08 | 2008-10-07 | Gabe Cherian | Oriented connections for leadless and leaded packages |
US6664615B1 (en) * | 2001-11-20 | 2003-12-16 | National Semiconductor Corporation | Method and apparatus for lead-frame based grid array IC packaging |
JP2005101031A (ja) * | 2003-09-22 | 2005-04-14 | Rohm Co Ltd | 半導体集積回路装置、及び電子機器 |
US7259460B1 (en) * | 2004-06-18 | 2007-08-21 | National Semiconductor Corporation | Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit package |
-
2007
- 2007-08-13 US US11/837,835 patent/US7906835B2/en active Active
-
2008
- 2008-08-07 EP EP08014165A patent/EP2026641A3/en not_active Ceased
- 2008-08-13 KR KR1020080079519A patent/KR20090017447A/ko active Search and Examination
- 2008-08-13 CN CN2008101310457A patent/CN101370352B/zh not_active Expired - Fee Related
- 2008-08-13 TW TW097130804A patent/TWI399146B/zh not_active IP Right Cessation
-
2009
- 2009-08-11 HK HK09107383.1A patent/HK1129524A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN101370352A (zh) | 2009-02-18 |
US7906835B2 (en) | 2011-03-15 |
US20090045508A1 (en) | 2009-02-19 |
HK1129524A1 (en) | 2009-11-27 |
TWI399146B (zh) | 2013-06-11 |
EP2026641A3 (en) | 2010-04-21 |
KR20090017447A (ko) | 2009-02-18 |
EP2026641A2 (en) | 2009-02-18 |
TW200938034A (en) | 2009-09-01 |
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TR01 | Transfer of patent right |
Effective date of registration: 20180507 Address after: Singapore Singapore Patentee after: Avago Technologies Fiber IP Singapore Pte. Ltd. Address before: Park Road, Irvine, California, USA, 16215, 92618-7013 Patentee before: Zyray Wireless Inc. |
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TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120208 Termination date: 20180813 |
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CF01 | Termination of patent right due to non-payment of annual fee |