KR970700369A - 집적회로패키지와 그 제조방법 - Google Patents
집적회로패키지와 그 제조방법 Download PDFInfo
- Publication number
- KR970700369A KR970700369A KR1019960703230A KR19960703230A KR970700369A KR 970700369 A KR970700369 A KR 970700369A KR 1019960703230 A KR1019960703230 A KR 1019960703230A KR 19960703230 A KR19960703230 A KR 19960703230A KR 970700369 A KR970700369 A KR 970700369A
- Authority
- KR
- South Korea
- Prior art keywords
- side portion
- mounting
- mounting region
- protrusion
- chip
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 239000004593 Epoxy Substances 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims 11
- 239000000758 substrate Substances 0.000 claims 6
- 238000007789 sealing Methods 0.000 claims 5
- 238000005452 bending Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
리드프레임스트립에 다이패드가 구비되고 돌출부가 그 배면측부로부터 돌출되도록 다이패드상에 형성되어 있다. 직접회로칩이 다이패드의 전면측부에 접착되고 다이패드에 일정한 리드프레임스트립의 부분에 리드로 연결된다. 다이패드, 칩과 리드가 모울드내에 배치되고 에폭시가 모울드내에 주입되어 다이패드, 칩과 리드를 밀봉한다. 돌출부는 다이패드의 배면측부에 대향된 모울드내면으로 부터 다이패드가 간격을 유지하도록 한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
Claims (21)
- 칩의 취부영역을 갖는 기재로 구성되고, 상기 취부영역은 칩을 취부하기 위한 제1측부와 상기 제1측부에서 대향된 제2측부를 가지며, 상기 취부영역에 상기 제2측부로부터 돌출된 돌출부가 구비됨을 특징으로 마운트.
- 청구범위 1항에 있어서, 상기 부재가 평면부를 형성하는 제1부분과 상기 평면부로부터 만곡되고 상기 취부영역을 포함하는 제2부분을 가지고, 상기 취부영역의 상기 제1측부가 상기 평면부를 향함을 특징으로 하는 마운트.
- 청구범위 1항에 있어서, 상기 돌출부가 상기 취부영역에 대하여 중심에 위치함을 특징으로 하는 마운트.
- 청구범위 1항에 있어서, 상기 돌출부가 상기 기재에 형성된 딤플로 구성됨을 특징으로 하는 마운트.
- 제1측부와 이 제1측부로부터 대향된 제2측부를 갖는 취부영역을 갖는 기재와, 상기 취부영역의 상기 제1측부에 고정된 집적회로 칩으로 구성되고, 상기 취부영역에 상기 제2측부로부터 돌출된 돌출부가 구비되어 있음을 특징으로 하는 집적회로 패키지.
- 청구범위 5항에 있어서, 상기 기재가 평면부를 형성하는 제1부분과 상기 평면부로부터 만곡되고 상기 취부 영역을 포함하는 제2부분을 가지고, 상기 취부영역의 상기 제1측부가 상기 평면부를 향함을 특징으로 하는 패키지.
- 청구범위 5항에 있어서, 상기 돌출부가 상기 취부영역에 대하여 중심에 위치함을 특징으로 하는 패키지.
- 청구범위 5항에 있어서, 상기 돌출부가 상기 기재에 형성된 딤플로 구성됨을 특징으로 하는 패키지.
- 청구범위 5항에 있어서, 상기 취부영역과 상기 칩이 수용되는 밀봉체가 구성되어 있음을 특징으로 하는 패키지.
- 청구범위 9항에 있어서, 상기 밀봉체가 플라스틱으로 구성됨을 특징으로 하는 패키지.
- 청구범위 9항에 있어서, 상기 밀봉체가 에폭시로 구성됨을 특징으로 하는 패키지.
- 청구범위 9항에 있어서, 상기 밀봉체가 외주면을 가지고 상기 제2측부가 상기 주면으로부터 일정한 간격을 두고 있으며, 상기 돌출부가 상기 제2측부로 부터 상기 주면으로 연장됨을 특징으로 하는 패키지.
- 집적회로 패키지의 제조방법에 있어서, 이 방법이 직접회로 칩이 배치되며 이 칩의 취부를 위한 제1측부와 상기 제1측부로 부터 대향된 제2측부를 갖는 취부영역을 갖는 기재를 제공하는 단계와, 상기 제2측부로부터 돌출된 돌출부를 형성하는 단계로 구성됨을 특징으로 하는 집적회로 패키지의 제조방법.
- 청구범위 13항에 있어서, 상기 기재와 평면부를 형성하고, 상기 취부영역의 상기 제1측부가 상기 평면부를 향하도록 상기 평면으로부터 상기 취부영역을 만곡시키는 단계가 구성되어 있음을 특징으로 하는 방법.
- 청구범위 13항에 있어서, 돌출부 형성단계가 상기 취부영역에 대하여 상기 돌출부를 중앙에 배치하는 단계로 구성됨을 특징으로 하는 방법.
- 청구범위 13항에 있어서, 돌출부 형성단계가 상기 기재에 딤플을 형성하는 단계로 구성됨을 특징으로 하는 방법.
- 청구범위 13항에 있어서, 상기 취부영역의 상기 제1측부에 선택된 칩을 고정시키는 단계가 구성되어 있음을 특징으로 하는 방법.
- 청구범위 17항에 있어서, 상기 취부영역과 상기 선택된 칩을 밀봉하는 단계가 구성되어 있음을 특징으로 하는 방법.
- 청구범위 18항에 있어서, 밀봉 단계가 플라스틱을 이용하여 수행됨을 특징으로 하는 방법.
- 청구범위 18항에 있어서, 밀봉 단계가 에폭시를 이용하여 수행됨을 특징으로 하는 방법.
- 청구범위 18항에 있어서, 밀봉 단계가 외주면을 갖는 밀봉체내에 상기 취부영역과 상기 선택된 칩을 수용하는 단계와, 상기 돌출부를 이용하여 상기 주면으로부터 제2측부를 일정간격으로 유지하는 단계로 구성됨을 특징으로 하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/324,717 | 1994-10-18 | ||
US08/324,717 US5578871A (en) | 1994-10-18 | 1994-10-18 | Integrated circuit package and method of making the same |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970700369A true KR970700369A (ko) | 1997-01-08 |
KR100428271B1 KR100428271B1 (ko) | 2004-07-12 |
Family
ID=23264783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960703230A KR100428271B1 (ko) | 1994-10-18 | 1995-10-13 | 집적회로패키지와그제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5578871A (ko) |
JP (1) | JP2002515176A (ko) |
KR (1) | KR100428271B1 (ko) |
WO (1) | WO1996013054A2 (ko) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3420827B2 (ja) * | 1994-04-28 | 2003-06-30 | ローム株式会社 | 半導体集積回路装置の製造方法及びリードフレーム |
JPH09153586A (ja) * | 1995-12-01 | 1997-06-10 | Texas Instr Japan Ltd | 半導体装置、その製造方法、及びリードフレーム |
KR100214544B1 (ko) * | 1996-12-28 | 1999-08-02 | 구본준 | 볼 그리드 어레이 반도체 패키지 |
TW398057B (en) * | 1998-07-30 | 2000-07-11 | Siliconware Precision Industries Co Ltd | A semiconductor device that has a chip seat with a bend part |
US6303985B1 (en) * | 1998-11-12 | 2001-10-16 | Micron Technology, Inc. | Semiconductor lead frame and package with stiffened mounting paddle |
JP3602997B2 (ja) * | 1999-12-15 | 2004-12-15 | 松下電器産業株式会社 | 半導体装置及び半導体装置の製造方法 |
TW541672B (en) * | 2001-11-09 | 2003-07-11 | Advanced Semiconductor Eng | Semiconductor chip manufacturing method, its product and leadframe |
JP2003197663A (ja) * | 2001-12-28 | 2003-07-11 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
DE10247610A1 (de) * | 2002-10-11 | 2004-04-29 | Micronas Gmbh | Elektronisches Bauelement mit einem Systemträger |
US20040113240A1 (en) * | 2002-10-11 | 2004-06-17 | Wolfgang Hauser | An electronic component with a leadframe |
JP2008085002A (ja) * | 2006-09-27 | 2008-04-10 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US7821116B2 (en) * | 2007-02-05 | 2010-10-26 | Fairchild Semiconductor Corporation | Semiconductor die package including leadframe with die attach pad with folded edge |
US20090152683A1 (en) * | 2007-12-18 | 2009-06-18 | National Semiconductor Corporation | Rounded die configuration for stress minimization and enhanced thermo-mechanical reliability |
US7808089B2 (en) * | 2007-12-18 | 2010-10-05 | National Semiconductor Corporation | Leadframe having die attach pad with delamination and crack-arresting features |
US8455988B2 (en) * | 2008-07-07 | 2013-06-04 | Stats Chippac Ltd. | Integrated circuit package system with bumped lead and nonbumped lead |
US20100123230A1 (en) * | 2008-11-20 | 2010-05-20 | Frederick Rodriguez Dahilig | Integrated circuit packaging system having bumped lead and method of manufacture thereof |
US9076776B1 (en) * | 2009-11-19 | 2015-07-07 | Altera Corporation | Integrated circuit package with stand-off legs |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4803540A (en) * | 1986-11-24 | 1989-02-07 | American Telephone And Telegraph Co., At&T Bell Labs | Semiconductor integrated circuit packages |
JPH01185958A (ja) * | 1988-01-21 | 1989-07-25 | Nec Corp | モールド型半導体装置 |
JPH02117162A (ja) * | 1988-10-27 | 1990-05-01 | Matsushita Electron Corp | 半導体装置 |
JPH0547979A (ja) * | 1991-08-21 | 1993-02-26 | Nec Corp | 樹脂封止型半導体装置 |
US5389739A (en) * | 1992-12-15 | 1995-02-14 | Hewlett-Packard Company | Electronic device packaging assembly |
-
1994
- 1994-10-18 US US08/324,717 patent/US5578871A/en not_active Expired - Fee Related
-
1995
- 1995-10-13 KR KR1019960703230A patent/KR100428271B1/ko not_active IP Right Cessation
- 1995-10-13 JP JP51376296A patent/JP2002515176A/ja active Pending
- 1995-10-13 WO PCT/IB1995/001018 patent/WO1996013054A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
JP2002515176A (ja) | 2002-05-21 |
WO1996013054A2 (en) | 1996-05-02 |
US5578871A (en) | 1996-11-26 |
KR100428271B1 (ko) | 2004-07-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR970700369A (ko) | 집적회로패키지와 그 제조방법 | |
KR900005586A (ko) | 반도체 디바이스 및 그 형성 방법 | |
KR930020649A (ko) | 리이드프레임 및 그것을 사용한 반도체집적회로장치와 그 제조방법 | |
KR960002782A (ko) | 패들없이 몰드된 플라스틱 반도체 칩 패키지 및 그 제조 방법 | |
KR940022807A (ko) | 반도체장치 및 반도체장치용 금형 | |
KR970053703A (ko) | 클립형 리드프레임과 이를 사용한 패키지의 제조방법 | |
KR950001998A (ko) | 소형 다이 패드를 갖고 있는 반도체 디바이스 및 이의 제조 방법 | |
US6396139B1 (en) | Semiconductor package structure with exposed die pad | |
US5874783A (en) | Semiconductor device having the inner end of connector leads displaced onto the surface of semiconductor chip | |
JP2857648B2 (ja) | 電子部品の製造方法 | |
KR930011318A (ko) | 반도체장치 및 그 제조방법 | |
KR970008546A (ko) | 반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법 | |
KR960002775A (ko) | 수지-봉합(resin-sealed) 반도체 소자 | |
KR920001694A (ko) | 중공(中空)의 칩 패키지 및 제조방법 | |
KR970024033A (ko) | 투명창을 구비한 반도체 패키지 및 그 제조방법 | |
KR100229223B1 (ko) | 리드 온 칩형 반도체 패키지 | |
KR970013255A (ko) | 요홈이 형성된 리드프레임 패드 및 그를 이용한 칩 패키지 | |
KR970024058A (ko) | 메탈 리드(lid)로 봉지된 패키지 | |
KR970072364A (ko) | Bga 반도체 패키지 | |
JPS6279637A (ja) | 半導体集積回路装置 | |
KR970072338A (ko) | 리드프레임에 금속판이 부착된 리드 온 칩형 반도체 칩 패키지 | |
KR100273226B1 (ko) | 버텀리드패키지 | |
KR950034719A (ko) | 리드 프레임 및 이 리드 프레임을 포함한 패키지 디바이스 제조 방법 | |
KR880007342A (ko) | 유니버샬 리드 프레임 캐리어 및 그 삽입물 | |
KR980006160A (ko) | 열 방출수단을 구비한 반도체 패캐이지 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |