KR970008546A - 반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법 - Google Patents

반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법 Download PDF

Info

Publication number
KR970008546A
KR970008546A KR1019950023471A KR19950023471A KR970008546A KR 970008546 A KR970008546 A KR 970008546A KR 1019950023471 A KR1019950023471 A KR 1019950023471A KR 19950023471 A KR19950023471 A KR 19950023471A KR 970008546 A KR970008546 A KR 970008546A
Authority
KR
South Korea
Prior art keywords
film
lead frame
manufacturing
pad
leadframe
Prior art date
Application number
KR1019950023471A
Other languages
English (en)
Other versions
KR0148080B1 (ko
Inventor
김상훈
심성민
홍인표
이상국
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950023471A priority Critical patent/KR0148080B1/ko
Priority to TW084111091A priority patent/TW288192B/zh
Priority to DE19540306A priority patent/DE19540306C1/de
Priority to CN95119249A priority patent/CN1080931C/zh
Priority to US08/557,540 priority patent/US5633206A/en
Priority to JP7296900A priority patent/JP2637715B2/ja
Publication of KR970008546A publication Critical patent/KR970008546A/ko
Application granted granted Critical
Publication of KR0148080B1 publication Critical patent/KR0148080B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

본 발명은 리드프레임 패드의 저면에 폴리아믹 에시드(polyamic acid)필름을 부착하고, 그 폴리아믹 에시드 필름을 열압착으로 폴리이미드 필름으로 형성시켜, 상기 리드프레임 패드와 폴리이미드 필름을 접착제에 의해 접착될 경우에 상기 두재료간의 박리를 방지할 수 있는 동시에 에칭법 또는 스탬핑법에 의해 그 폴리이미드 필름에 딤플을 형성하여 성형수지와 리드프레임간의 결합력을 증대시킬 수 있는 것이다.

Description

반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5A도는 본 발명에 의한 리드프레임 패드의 저면에 폴리이미드 필름이 부착된 리드프레임의 저면도, 제5B도는 제5A도의 D-D선 단면도.

Claims (8)

  1. 리드프레임 패드의 필름을 접착하는 방법으로, 리드프레임을 준비하여 그 리드프레임 패드에 필름을 부착하는 단계와; 열발생장치를 이용하여 상기 필름을 상기 리드프레임 패드에 열압착하는 단계를 포함하는 것을 특징으로 하는 반도체 리드프레임 제조방법.
  2. 제1항에 있어서, 상기 열압착되는 온도가 350∼420℃인 것을 특징으로 하는 반도체 리드프레임 제조방법.
  3. 제1항에 있어서, 상기 필름이 폴리아믹 애시드 필름인 것을 특징으로 하는 반도체 리드프레임 제조방법.
  4. 제1항에 있어서, 상기 필름이 상기 리드프레임 패드의 저면에 부착되는 것을 특징으로 하는 반도체 리드프레임 제조방법.
  5. 제3항에 있어서, 상기 폴리아믹 애시드 필름이 열압착된 후에 폴리이미드 필름으로 변형되는 것을 특징으로 하는 반도체 리드프레임 제조방법.
  6. 리드프레임을 준비하여 그 리드프레임 패드에 필름을 부착하는 단계와; 열발생장치를 이용하여 상기 필름을 상기 리드프레임 패드에 열압착하는 단계; 그 리드프레임 패드의 상면에 칩을 접착하는 단계와; 그 칩상에 형성된 본딩패드들과 그들에 대응되는 내부리드들을 전기적 연결하는 단계와; 그 칩이 탑재된 리드프레임의 소정영역을 성형하는단계를 포함하는 것을 특징으로 하는 반도체 리드프레임 제조방법을 이용한 반도체 칩 패키지 제조방법.
  7. 제6항에 있어서, 상기 필름에 적어도 하나 이상의 홈이 형성된 것을 특징으로 하는 반도체 리드프레임 제조방법을 이용한 반도체 칩 패키지 제조방법.
  8. 제6항에 있어서, 상기 리드프레임 패드상에 필름이 형성된 것을 특징으로 하는 반도체 리드프레임 제조방법을 이용한 반도체 칩 패키지 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950023471A 1995-07-31 1995-07-31 반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법 KR0148080B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950023471A KR0148080B1 (ko) 1995-07-31 1995-07-31 반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법
TW084111091A TW288192B (en) 1995-07-31 1995-10-20 Process for manufacturing lead frame for semiconductor package
DE19540306A DE19540306C1 (de) 1995-07-31 1995-10-28 Verfahren zur Herstellung von Leiterrahmen für Halbleiterbauelemente
CN95119249A CN1080931C (zh) 1995-07-31 1995-11-14 用于生产半导体封装引线框架的工艺
US08/557,540 US5633206A (en) 1995-07-31 1995-11-14 Process for manufacturing lead frame for semiconductor package
JP7296900A JP2637715B2 (ja) 1995-07-31 1995-11-15 半導体リードフレームの製造方法およびそれを利用した半導体チップパッケージの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950023471A KR0148080B1 (ko) 1995-07-31 1995-07-31 반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법

Publications (2)

Publication Number Publication Date
KR970008546A true KR970008546A (ko) 1997-02-24
KR0148080B1 KR0148080B1 (ko) 1998-08-01

Family

ID=19422430

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950023471A KR0148080B1 (ko) 1995-07-31 1995-07-31 반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법

Country Status (6)

Country Link
US (1) US5633206A (ko)
JP (1) JP2637715B2 (ko)
KR (1) KR0148080B1 (ko)
CN (1) CN1080931C (ko)
DE (1) DE19540306C1 (ko)
TW (1) TW288192B (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260550A (ja) * 1996-03-22 1997-10-03 Mitsubishi Electric Corp 半導体装置
US5929511A (en) * 1996-07-15 1999-07-27 Matsushita Electronics Corporation Lead frame for resin sealed semiconductor device
US5922167A (en) * 1997-01-16 1999-07-13 Occidential Chemical Corporation Bending integrated circuit chips
TW434760B (en) * 1998-02-20 2001-05-16 United Microelectronics Corp Interlaced grid type package structure and its manufacturing method
US6249045B1 (en) 1999-10-12 2001-06-19 International Business Machines Corporation Tented plated through-holes and method for fabrication thereof
US6929485B1 (en) * 2004-03-16 2005-08-16 Agilent Technologies, Inc. Lead frame with interdigitated pins
DE102006028815B3 (de) * 2006-06-21 2007-08-30 Hansa Tronic Gmbh Verfahren zur Herstellung eines elektrischen Hybridbauteils
KR101150020B1 (ko) * 2010-07-15 2012-05-31 엘지이노텍 주식회사 리드 프레임
CN102501343B (zh) * 2011-11-18 2014-07-16 毕翊 半导体引线框架除溢胶全自动生产线
KR20170096258A (ko) * 2016-02-15 2017-08-24 삼성전자주식회사 검사장치
CN115599027B (zh) * 2022-12-16 2023-03-14 西北工业大学 一种低维飞行器芯片微系统、制备及控制方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369090A (en) * 1980-11-06 1983-01-18 Texas Instruments Incorporated Process for etching sloped vias in polyimide insulators
US4890157A (en) * 1986-01-31 1989-12-26 Texas Instruments Incorporated Integrated circuit product having a polyimide film interconnection structure
US4709468A (en) * 1986-01-31 1987-12-01 Texas Instruments Incorporated Method for producing an integrated circuit product having a polyimide film interconnection structure
JPS62266852A (ja) * 1986-05-14 1987-11-19 Mitsubishi Electric Corp 半導体集積回路装置
JPS6442847A (en) * 1987-08-10 1989-02-15 Toshiba Corp Lead frame
JP2587074B2 (ja) * 1987-12-25 1997-03-05 日東電工株式会社 半導体装置
US5070039A (en) * 1989-04-13 1991-12-03 Texas Instruments Incorporated Method of making an integrated circuit using a pre-served dam bar to reduce mold flash and to facilitate flash removal
US4916519A (en) * 1989-05-30 1990-04-10 International Business Machines Corporation Semiconductor package
JPH0320066A (ja) * 1989-06-16 1991-01-29 Matsushita Electron Corp 半導体パッケージ部品
US5208188A (en) * 1989-10-02 1993-05-04 Advanced Micro Devices, Inc. Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
US5313102A (en) * 1989-12-22 1994-05-17 Texas Instruments Incorporated Integrated circuit device having a polyimide moisture barrier coating
US5122858A (en) * 1990-09-10 1992-06-16 Olin Corporation Lead frame having polymer coated surface portions
EP0504634A3 (en) * 1991-03-08 1994-06-01 Japan Gore Tex Inc Resin-sealed semiconductor device containing porous fluorocarbon resin
JP2994171B2 (ja) * 1993-05-11 1999-12-27 株式会社東芝 半導体装置の製造方法および封止用部材の製造方法
US5384690A (en) * 1993-07-27 1995-01-24 International Business Machines Corporation Flex laminate package for a parallel processor
US5429992A (en) * 1994-05-25 1995-07-04 Texas Instruments Incorporated Lead frame structure for IC devices with strengthened encapsulation adhesion

Also Published As

Publication number Publication date
JPH0945833A (ja) 1997-02-14
CN1142122A (zh) 1997-02-05
TW288192B (en) 1996-10-11
KR0148080B1 (ko) 1998-08-01
CN1080931C (zh) 2002-03-13
DE19540306C1 (de) 1996-11-28
US5633206A (en) 1997-05-27
JP2637715B2 (ja) 1997-08-06

Similar Documents

Publication Publication Date Title
CN103531581A (zh) 多芯片模块
KR970008546A (ko) 반도체 리드프레임 제조방법 및 그를 이용한 반도체 칩 패키지 제조방법
JPS61166051A (ja) 樹脂封止型半導体装置
KR930024140A (ko) 반도체장치 및 그 제조방법
KR920007155A (ko) 반도체 장치 및 그 제조 방법
KR900001004A (ko) 플라스틱 캡슐형 멀티칩 하이브리드 집적회로
KR910001949A (ko) 무플래그 리드프레임, 피키지 및 방법
KR950021455A (ko) 수지 봉지형 반도체 장치
JPS57112055A (en) Integrated circuit package
KR970077602A (ko) 칩접착부가 일체형으로 형성된 타이바를 갖는 패드리스 리드프레임과 이를 이용한 반도체 칩 패키지
JPS63107152A (ja) 樹脂封止型電子部品
JPH02127092A (ja) Ｉｃカードモジユール
JPH027469Y2 (ko)
KR200179421Y1 (ko) 적층형 반도체 패캐이지
KR950002001A (ko) 반도체 패키지
JPH05275570A (ja) 半導体装置
KR870000753A (ko) 수지봉합형 반도체장치
KR970063687A (ko) 더미리드와 히트싱크의 직접 전기적 연결 구조를 갖는 파워 패키지
KR970013255A (ko) 요홈이 형성된 리드프레임 패드 및 그를 이용한 칩 패키지
KR970024058A (ko) 메탈 리드(lid)로 봉지된 패키지
KR920010862A (ko) 반도체 장치 및 이것에 사용되는 리드프레임
KR950004510A (ko) 버텀리드형 반도체 패키지의 구조 및 그 제조방법
JPS63293955A (ja) 樹脂封止型半導体装置
KR960002764A (ko) 캐패시터를 구비한 반도체 패키지 및 그 제조방법
KR960703274A (ko) 분리 실리콘기판을 사용하여 전기적 열적으로 향상된 팩키지(electrically and thermally enhanced package using a separate silicon substrate)

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120430

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee