KR970067772A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR970067772A
KR970067772A KR1019960059474A KR19960059474A KR970067772A KR 970067772 A KR970067772 A KR 970067772A KR 1019960059474 A KR1019960059474 A KR 1019960059474A KR 19960059474 A KR19960059474 A KR 19960059474A KR 970067772 A KR970067772 A KR 970067772A
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South Korea
Prior art keywords
source
drain
bit line
mos transistor
pairs
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KR1019960059474A
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English (en)
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KR100299750B1 (ko
Inventor
후카시 모리시타
시케키 도미시마
가즈타니 아리모토
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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Publication of KR970067772A publication Critical patent/KR970067772A/ko
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Publication of KR100299750B1 publication Critical patent/KR100299750B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dram (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

DRAM의 메모리 셀에 포함된 MOS트렌지스터의 보디에 축적되는 캐리어가 서브스레숄드 리이크전류를 증대시켜, 메모리 셀의 테이터보지 시간을 단축한다. 보디 리플레쉬모드시에 비트선 전위 VBL이 보디리플레쉬전위 VBR로 되는 것으로 비트선 프리차지/이퀼라이즈회로 111c를 통해 비트 선 쌍 72b에 보디 리플레쉬 전위VBR이 공급되어 메모리 셀 72c에서의 n채널 MOS 트랜지스터 72cb의 보디에 축적된 캐리어가 비트선 쌍 72b로 배출된다.

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시의 형태 1의 DRAM을 나타내는 블럭도이다.

Claims (3)

  1. 한 쪽 및 다른 쪽의 전극을 가지는 커패시터와, 한 쪽 및 다른 쪽의 소스/드레인, 한 쪽 및 다른 쪽의 소스/드레인에 끼워지는 플로우팅한 보디 및 게이트를 가지고, 상기 한 쪽의 소스/드레인이 상기 커패시터의 다른 쪽의 전극에 접속되는 MOS 트랜지스터를 포함하는 메모리셀, 및 상기 MOS트랜지스터의 보디에 축적하는 전하를 배출하기 위한 전하 배출수단을 구비하는 반도체 기억장치.
  2. 제1항에 있어서, MOS 트랜지스터의 다른 쪽의 소스/드레인에 접속되는 제1의 비트선을 더 구비하고, 전하 배출수단은 MOS트랜지스터의 보디에 축적하는 전하를 배출하기 위한 보디리플레쉬 전위를 상기 제1의 비트선에 공급하는 보디플레쉬 전위공급수단을 가지는 반도체 기억장치.
  3. 복수행 및 복수열로 배치되어, 한 쪽 및 다른 쪽의 전극을 가지는 커패시터와, 한 쪽 및 다른쪽의 소스/드레인, 한쪽 및 다른쪽의 소스/드레인에 끼워지는 보디 및 게이트를 가지고, 상기 한쪽의 소스/드레인이 상기 커래시터의 다른 쪽의 전극에 접속되는 MOS트랜지스터를 각각이 포함하는 복수의 메모리셀과, 복수열로 배치되어, 대응한 열로 배치되는 메모리셀의 다른 쪽의 소스/드레인이 접속되는 복수의 비트선쌍과, 상기 복수의 비트선쌍의 각각에 접속되어, 대응한 비트선쌍에 생긴 전위차를 증폭함과 동시에, 보디 리플레쉬는 대응된 비트선쌍의 한 쪽의 비트선의 전위를 보디리플레쉬전위로 하는 복수의 센스앰프와, I/O선쌍과, 상기 복수의 비트선쌍과 상기 I/O선쌍과의 사이에 각각 접속되어, 선택적으로 1개의 비트선쌍과 상기 I/O선쌍을 도통상태로 함과 동시에, 보디 리플레쉬때는 상기 복수의 비트선쌍 중 복수쌍과 상기 I/O선쌍을 도통상태로 하는 , 복수의 게이트 수단을 구비하는 반도체 기억장치.
KR1019960059474A 1996-03-04 1996-11-29 반도체 기억장치 KR100299750B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP04586496A JP3759648B2 (ja) 1996-03-04 1996-03-04 半導体記憶装置
JP96-045864 1996-03-04

Publications (2)

Publication Number Publication Date
KR970067772A true KR970067772A (ko) 1997-10-13
KR100299750B1 KR100299750B1 (ko) 2001-11-30

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US (2) US5877978A (ko)
JP (1) JP3759648B2 (ko)
KR (1) KR100299750B1 (ko)
DE (1) DE19649876C2 (ko)

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US6081443A (en) 2000-06-27
DE19649876A1 (de) 1997-11-06
KR100299750B1 (ko) 2001-11-30
DE19649876C2 (de) 2001-09-27
US5877978A (en) 1999-03-02

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