KR960026257A - 다층 텡스텐 침착 방법 - Google Patents

다층 텡스텐 침착 방법 Download PDF

Info

Publication number
KR960026257A
KR960026257A KR1019950067127A KR19950067127A KR960026257A KR 960026257 A KR960026257 A KR 960026257A KR 1019950067127 A KR1019950067127 A KR 1019950067127A KR 19950067127 A KR19950067127 A KR 19950067127A KR 960026257 A KR960026257 A KR 960026257A
Authority
KR
South Korea
Prior art keywords
layer
tungsten
deposition rate
deposited
layers
Prior art date
Application number
KR1019950067127A
Other languages
English (en)
Inventor
맨신 머챈트 세일레쉬
쿠마 낸다 애런
쿠마 로이 프라디프
Original Assignee
일라이 웨이스
에이티앤드티 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 일라이 웨이스, 에이티앤드티 코포레이션 filed Critical 일라이 웨이스
Publication of KR960026257A publication Critical patent/KR960026257A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Coating By Spraying Or Casting (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

본 발명은 3개 이상, 바람직하게는 5 내지 7개의 텅스텐 층을 접촉 구멍내에 칩착시켜 층으로 이루어진 플러그를 형성시키므로써, 원치않은 텅스텐 확산 형성을 피하도록 텅스텐 플러그에 관한 것이다. 특히 유용한 실시태양에서, 상기 층은 빠르고 느린 침착 속도로 교대로 침착시킨다.

Description

다층 텅스텐 침착 방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본원에 개시된 방법에 따라(원도우 또는 바이어 레벨에서)텅스텐 플러그를 형성시키는 단계를 나타내는 흐름도이다.

Claims (21)

  1. 3개 이상의 연속적인 텅스텐 층을 접촉 구멍내에 침착시킴을 포함하고; 이때 상기 각 층은 이전이 층을 접착시킨 속도와 상이한 침가속도로 침착되고, 40Å/초보다 큰 빠른 침착속도 및 40Å/초 미만인 느린 침착속도로 교대로 침착되는 텅스텐 플러그 제조 방법.
  2. 제1항에 있어서, 상기 3개 이상의 연속적인 텅스텐 층 각각을 텅스텐 헥사플루오라이드의 소수 환원에 의해 침착시키는 방법.
  3. 제2항에 있어서, 상기 각 층의 침착 공정이 약 10초 내지 약 2분의 비성장 기간만큼 분리되는 방법.
  4. 제1항에 있어서, 5개 이상의 연속적인 텅스텐 층을 침착시키는 방법.
  5. 제3항에 있어서, 상기 5개 이상의 연속적인 텅스텐 층을 침착시키는 방법.
  6. 전도성 층, 상기 전도성 층상에 형성된 절연체 층 및 상기 전도성 층 부분을 노출시키기 위해 절연체 층중에 형성시킨 접촉 구멍을 갖는 기재를 제공하고; 상기 접촉 구멍내에 3개 이상의텅스텐 츠을 침착시켜 적어도 거의 접촉 구멍을 충진시키므로써, 기재의 전도성 층과 또다른 전도성 요소 사이를 전기적으로 연결시킬 수 있는 텅스텐 플러그 형성시킴을 포함하는 전자 장치의 제조 방법.
  7. 제6항에 있어서, 5개 아상의 텅스텐 층을 상기 접촉 구멍내에 침착시키는 방법.
  8. 제6항에 있어서, 상기 연속적인 각 텅스텐 층을 침착시키는 단계가 H2에 의해 WF6를 환원시킴을 포함하는 방법.
  9. 제6항에 있어서, 상기 3개 이상의 각 텅스텐 층을 이전의 층을 침착시킨 속도와 상이한 침착 속도로 침차시키는 방법.
  10. 제9항에 있어서, 상기 3개 이상의 텅스텐 층을 40/초보다 큰 빠른 침착 속도 및 40Å/초 미만의 느린 침착 속도로 교대로 침착시키는 방법.
  11. (a)40Å/초보다 큰 침착 속도로 WF6의 H2환원에 의해 텅스텐 층을 침착시키는 단계; (b) 40Å/초 미만의 침착 속도로 WF6의 H2환원에 의해 텅스텐 층을 침착시키는 단계; (c) 단계(a) 및 (b)를 적어도 거의 접촉 구멍을 충진시키기에 충부한 횟수로 교대로 반복하여, 층으로 이루어진 텅스텐 플러그를 형성시키는 단계를 포함하는, 기재중에 형성된 접촉 구멍내에 텅스텐 플러그를 제조하는 방법.
  12. 제11항에 있어서, 상기 단계 (a)가 기재를 함유하는 챔버의 전체 압력 약 10 내지 약 100토르하에 상기 챔버중으로 H2를 약 6000 내지 약 7500SCCM의 유동속도로 도입하고, 상기 챔버중으로 WF6를 약 300 내지 약 500SCCM의 유동속도로 도입함을 포함하는 방법.
  13. 제11항에 있어서, 상기 단계 (b)가 기재를 함유하는 챔버의 전체 압력 약 10 내지 약 100토르하에 상기 챔버중으로 H2를 약 3000 내지 약 5000SCCM의 유동속도로 도입하고, 상기 챔버중으로 WF6를 약 100 내지 약 300SCCM의 유동속도로 도입함을 포함하는 방법.
  14. 제11항에 있어서, 상기 층으로 이루어진 텅스텐 플러그가 5개 이상의 텅스텐 층을 포함하는 방법.
  15. 텅스텐의 제1층을 제1침착 속도로 WF6의 H2환원에 의해 침착시키고, 텅스텐의 제2층을 상기 제1침착 속도보다 느린 제2침착 속도로 WF6의 H2환원에 의해 침착시키고; 텅스텐 제3층을 상기 제2침착 속도보다 빠른 제3침착 속도로 WF6의 H2환원에 의해 침착시킴을 포함하는, 기재중에 형성된 첩촉 구멍내에 텅스텐 플러그를 제조하는 방법.
  16. 제15항에 있어서, 텅스텐의 제4층을 상기 제3침착 속도보다 느린 제4침착 속도로 WF6의 H2환원에 의해 침착시키고; 텅스텐의 제5층을 상기 제4침착 속도보다 빠른 제5침착 속도로 WF6의 H2환원에 의해 침착시킴을 또한 포함하는 방법.
  17. 제16항에 있어서, 텅스텐의 지6층을 상기 제5침착 속도보다 느린 제6침착 속도로 WF6의 H2환원에 의해 침착시키고; 텅스텐의 제 7층을 상기 제6침착 속도보다 빠른 제7침착 속도로 WF6의 H2환원에 의해 침착시킴을 또한 포함하는 방법.
  18. 제17항에 있어서, 지 1,3,5 및 제7침착 속도가 40Å/초보다 큰 방법.
  19. 제1층, 제1층상에 형성된 절연체 층 및 절연체 층중에 형성된 접촉 구멍을 갖고 제1층 부분이 노출된 기제를 제공하고; 상기 접촉 구멍내에 5개 이상의 텅스텐 층을 침착시켜 적어도 거의 접촉 구멍을 충진시킴을 포함하는 전자 장치의 제조 방법.
  20. 제19항에 있어서, 상기 5개 이상의 층을 교대로 빠르고 느린 침착 속도로 침착시키는 방법.
  21. 제1층; 제2층; 및 상기 제1층과 상기 제2층 사이를 전기 접촉시키며 5개 이상의 층을 갖는 텅스텐 플러그를 포함하는 상호연결 구조물을 포함하는 전자 장치.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950067127A 1994-12-30 1995-12-29 다층 텡스텐 침착 방법 KR960026257A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/366,529 US5489552A (en) 1994-12-30 1994-12-30 Multiple layer tungsten deposition process
US08/366,529 1994-12-30

Publications (1)

Publication Number Publication Date
KR960026257A true KR960026257A (ko) 1996-07-22

Family

ID=23443406

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950067127A KR960026257A (ko) 1994-12-30 1995-12-29 다층 텡스텐 침착 방법

Country Status (5)

Country Link
US (1) US5489552A (ko)
EP (1) EP0720211A3 (ko)
JP (1) JPH08232079A (ko)
KR (1) KR960026257A (ko)
TW (1) TW344893B (ko)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950012738B1 (ko) * 1992-12-10 1995-10-20 현대전자산업주식회사 반도체소자의 텅스텐 콘택 플러그 제조방법
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
US20030199179A1 (en) * 1993-11-16 2003-10-23 Formfactor, Inc. Contact tip structure for microelectronic interconnection elements and method of making same
JP2737764B2 (ja) * 1995-03-03 1998-04-08 日本電気株式会社 半導体装置及びその製造方法
US5643632A (en) * 1995-10-13 1997-07-01 Mosel Vitelic, Inc. Tungsten chemical vapor deposition process for suppression of volcano formation
US6017818A (en) * 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US5656545A (en) * 1996-02-26 1997-08-12 Taiwan Semiconductor Manufacturing Company, Ltd Elimination of tungsten dimple for stacked contact or via application
US5672543A (en) * 1996-04-29 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Volcano defect-free tungsten plug
US20040224501A1 (en) * 1996-05-22 2004-11-11 Yung-Tsun Lo Manufacturing method for making tungsten-plug in an intergrated circuit device without volcano phenomena
US5700726A (en) * 1996-06-21 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Multi-layered tungsten depositions for contact hole filling
US5843625A (en) * 1996-07-23 1998-12-01 Advanced Micro Devices, Inc. Method of reducing via and contact dimensions beyond photolithography equipment limits
US5804249A (en) * 1997-02-07 1998-09-08 Lsi Logic Corporation Multistep tungsten CVD process with amorphization step
US5913146A (en) * 1997-03-18 1999-06-15 Lucent Technologies Inc. Semiconductor device having aluminum contacts or vias and method of manufacture therefor
US5956609A (en) * 1997-08-11 1999-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
KR100272523B1 (ko) * 1998-01-26 2000-12-01 김영환 반도체소자의배선형성방법
US6136690A (en) 1998-02-13 2000-10-24 Micron Technology, Inc. In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications
US6982226B1 (en) 1998-06-05 2006-01-03 Agere Systems Inc. Method of fabricating a contact with a post contact plug anneal
JP2000265272A (ja) * 1999-01-13 2000-09-26 Tokyo Electron Ltd タングステン層の形成方法及びタングステン層の積層構造
US6294468B1 (en) * 1999-05-24 2001-09-25 Agere Systems Guardian Corp. Method of chemical vapor depositing tungsten films
US6316132B1 (en) 1999-09-02 2001-11-13 Xilinx, Inc. Structure and method for preventing barrier failure
US6309966B1 (en) * 1999-09-03 2001-10-30 Motorola, Inc. Apparatus and method of a low pressure, two-step nucleation tungsten deposition
KR100364257B1 (ko) 1999-12-06 2002-12-11 삼성전자 주식회사 텅스텐 화학 기상 퇴적방법 및 텅스텐 플러그 형성방법
US6569699B1 (en) * 2000-02-01 2003-05-27 Chartered Semiconductor Manufacturing Ltd. Two layer mirror for LCD-on-silicon products and method of fabrication thereof
US6358844B1 (en) * 2000-06-01 2002-03-19 Taiwan Semiconductor Manufacturing, Company, Ltd Tungsten deposition process with dual-step nucleation
WO2002010472A1 (fr) * 2000-07-28 2002-02-07 Tokyo Electron Limited Procede de formage de film
JP2003142484A (ja) * 2001-10-31 2003-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
US8461681B2 (en) * 2007-04-27 2013-06-11 Medtronic, Inc. Layered structure for corrosion resistant interconnect contacts
US8129270B1 (en) 2008-12-10 2012-03-06 Novellus Systems, Inc. Method for depositing tungsten film having low resistivity, low roughness and high reflectivity
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8691687B2 (en) * 2010-01-07 2014-04-08 International Business Machines Corporation Superfilled metal contact vias for semiconductor devices
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP6273257B2 (ja) 2012-03-27 2018-01-31 ノベラス・システムズ・インコーポレーテッドＮｏｖｅｌｌｕｓ Ｓｙｓｔｅｍｓ Ｉｎｃｏｒｐｏｒａｔｅｄ タングステンによるフィーチャ充填
US9082826B2 (en) 2013-05-24 2015-07-14 Lam Research Corporation Methods and apparatuses for void-free tungsten fill in three-dimensional semiconductor features
US9349637B2 (en) 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
WO2016046909A1 (ja) * 2014-09-24 2016-03-31 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、半導体装置およびプログラム
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US10566211B2 (en) 2016-08-30 2020-02-18 Lam Research Corporation Continuous and pulsed RF plasma for etching metals
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
JP2022510428A (ja) 2018-12-05 2022-01-26 ラム リサーチ コーポレーション ボイドフリーの低応力充填
CN113053804B (zh) * 2021-03-10 2023-02-21 中国科学院微电子研究所 一种钨复合膜层及其生长方法、单片3dic
CN115910917B (zh) * 2023-01-05 2023-06-02 广州粤芯半导体技术有限公司 金属钨膜及其制备方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532702A (en) * 1983-11-04 1985-08-06 Westinghouse Electric Corp. Method of forming conductive interconnection between vertically spaced levels in VLSI devices
US4629635A (en) * 1984-03-16 1986-12-16 Genus, Inc. Process for depositing a low resistivity tungsten silicon composite film on a substrate
JPS62216224A (ja) * 1986-03-17 1987-09-22 Fujitsu Ltd タングステンの選択成長方法
JPS62260340A (ja) * 1986-05-06 1987-11-12 Toshiba Corp 半導体装置の製造方法
EP0252667B1 (en) * 1986-06-30 1996-03-27 Nihon Sinku Gijutsu Kabushiki Kaisha Chemical vapour deposition methods
JP2582596B2 (ja) * 1987-12-17 1997-02-19 富士通株式会社 半導体装置の製造方法
JP2511503B2 (ja) * 1988-08-22 1996-06-26 沖電気工業株式会社 タングステン膜の形成方法
US4985371A (en) * 1988-12-09 1991-01-15 At&T Bell Laboratories Process for making integrated-circuit device metallization
US5233223A (en) * 1989-01-09 1993-08-03 Nec Corporation Semiconductor device having a plurality of conductive layers interconnected via a tungsten plug
JP2821157B2 (ja) * 1989-01-30 1998-11-05 株式会社日立製作所 配線形成方法
US5143861A (en) * 1989-03-06 1992-09-01 Sgs-Thomson Microelectronics, Inc. Method making a dynamic random access memory cell with a tungsten plug
JPH0360126A (ja) * 1989-07-28 1991-03-15 Toshiba Corp 半導体装置の製造方法
KR930000309B1 (ko) * 1989-11-22 1993-01-15 삼성전자 주식회사 반도체 장치의 제조방법
JPH04363024A (ja) * 1990-11-30 1992-12-15 Toshiba Corp 半導体装置の製造方法
JPH05347272A (ja) * 1991-01-26 1993-12-27 Sharp Corp 半導体装置の製造方法
JP2660359B2 (ja) * 1991-01-30 1997-10-08 三菱電機株式会社 半導体装置
JPH04307933A (ja) * 1991-04-05 1992-10-30 Sony Corp タングステンプラグの形成方法
US5164330A (en) * 1991-04-17 1992-11-17 Intel Corporation Etchback process for tungsten utilizing a NF3/AR chemistry
JPH053170A (ja) * 1991-06-24 1993-01-08 Sony Corp ブランケツトタングステンプラグ形成法
JPH05160067A (ja) * 1991-07-23 1993-06-25 Seiko Epson Corp 半導体装置およびその製造方法
US5200360A (en) * 1991-11-12 1993-04-06 Hewlett-Packard Company Method for reducing selectivity loss in selective tungsten deposition
JPH05152292A (ja) * 1991-11-30 1993-06-18 Sony Corp 配線形成方法
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
CA2067565C (en) * 1992-04-29 1999-02-16 Ismail T. Emesh Deposition of tungsten
GB9219281D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
US5232873A (en) * 1992-10-13 1993-08-03 At&T Bell Laboratories Method of fabricating contacts for semiconductor devices
US5272112A (en) * 1992-11-09 1993-12-21 Genus, Inc. Low-temperature low-stress blanket tungsten film

Also Published As

Publication number Publication date
JPH08232079A (ja) 1996-09-10
EP0720211A2 (en) 1996-07-03
US5489552A (en) 1996-02-06
EP0720211A3 (en) 1997-03-05
TW344893B (en) 1998-11-11

Similar Documents

Publication Publication Date Title
KR960026257A (ko) 다층 텡스텐 침착 방법
KR960039281A (ko) 반도체 장치의 배선 구조 및 그 제조 방법
KR950034564A (ko) 반도체 장치의 기계화학적 연마방법
TW346658B (en) Method for manufacturing capacitor for semiconductor device
KR100283110B1 (ko) 반도체소자의 금속배선 형성방법
CN1074857C (zh) 用于形成半导体器件金属布线的方法
US5247204A (en) Semiconductor device having multilayer interconnection structure
US6906370B1 (en) Semiconductor component having a material reinforced contact area
DE19713501C2 (de) Verfahren zum Verbinden leitender Schichten in einem Halbleiterbauteil
KR20010003760A (ko) 반도체 소자의 배선 형성방법
KR960004078B1 (ko) 금속박막 적층구조를 사용한 콘택 형성방법
KR100973261B1 (ko) 반도체소자의 텅스텐 플러그 형성 방법
KR960042952A (ko) 금속배선간 접촉을 위한 접촉창 및 그 형성방법
KR890013738A (ko) 집적회로 기판상의 소자들을 금속화층에 접속하는 방법
KR970052242A (ko) 반도체 소자의 금속배선 형성방법
KR20030002787A (ko) 반도체 소자의 금속 플러그 형성방법
KR970018413A (ko) 반도체장치의 다층배선 형성방법
KR950015606A (ko) 반도체 소자의 금속배선 형성방법
JPS57201072A (en) Semiconductor device and manufacture thereof
KR970052328A (ko) 반도체 소자의 도선층 형성 방법
JPH0480917A (ja) 半導体装置の製造方法
JPH08203895A (ja) 高圧リフローによる孔の埋め込み方法
KR970052930A (ko) 반도체 소자의 금속배선막 형성방법
TW351000B (en) Method of manufacturing damascene interconnection in multi-layer dielectric
KR960005797A (ko) 반도체소자 배선 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application