CN1074857C - 用于形成半导体器件金属布线的方法 - Google Patents

用于形成半导体器件金属布线的方法

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CN1074857C
CN1074857C CN95118735A CN95118735A CN1074857C CN 1074857 C CN1074857 C CN 1074857C CN 95118735 A CN95118735 A CN 95118735A CN 95118735 A CN95118735 A CN 95118735A CN 1074857 C CN1074857 C CN 1074857C
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conductive layer
tungsten
insulating barrier
layer
contact hole
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崔樑圭
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SK Hynix Inc
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Abstract

一种用于在高集成度半导体器件中形成与下导电层接触的上金属布线的方法。此方法包括在下绝缘层上形成金属布线，在绝缘层上形成一接触孔以暴露出下导电层，以及在接触孔中生长金属层以填满此接触孔等步骤，从而金属布线层可与下导电层相接触。

Description

用于形成半导体器件金属布线的方法
本发明涉及一种用于形成半导体器件金属布线的方法，尤其涉及一种在集成度高的半导体器件中形成与下导电层接触的上金属布线的方法。
半导体器件的集成度不断增加导致了高宽比(即接触孔深度与接触孔宽度的比值)不断增加。当填满接触孔并用作上布线的金属布线由低熔点的铝制成时，此高宽比的增加引起电迁移和应力迁移特性的下降。因为高宽比增加引起拓扑变得更高，可能在用淀积方法填满接触孔中的金属层的步骤中于接触孔中形成空隙。此外，在形成图案的步骤中可能留有不需要的残留物质。这样，会在相邻图案之间产生短路。当金属布线由钨制成时，会形成劣质图形和产生微粒。结果，很可能产生短路。
典型地，通过形成一接触孔，形成填满此接触孔的金属层及然后刻蚀金属层而完成此上金属布线。用于形成与下导电层接触的金属布线的通常方法将参考图1A到1C进行描述。
参考图1A，示出已确定扩散区2的半导体衬底1。在半导体衬底1上已形成绝缘层3。
如图1B所示，在绝缘层3上，形成接触掩模4。用此接触掩模4，在绝缘层3的相应于接触孔的区域进行刻蚀，从而形成接触孔5。通过接触孔5，露出了扩散区2。
然后，如图1C所示，除去接触掩模4。在如此得到的结构上，淀积金属层。用金属布线掩模(未示出)对金属层进行刻蚀，从而形成金属布线6。
然而，这种方法只适用于在绝缘层是平面形表面的条件下在接触孔形成后使金属布线与下扩散区接触。当绝缘层具有高拓扑表面时，在金属布线形成后可能留下一部分金属层。由于在接触孔中形成的空隙也会产生不良接触。
因此，本发明的目的是为了解决上述问题并提供一种用于形成半导体器件金属布线的方法，它能通过在绝缘层中形成接触孔之前在绝缘层上先形成金属布线，以及在接触孔形成以后选择性地生长一金属层来填满此接触孔，从而防止金属布线短路或断开。
依据一个方面，本发明提供了一种用于形成半导体器件金属布线的方法，包括以下步骤：在半导体衬底上形成第一导电层；在第一导电层形成获得的结构上形成绝缘层，然后在绝缘层上形成金属布线掩模；用此金属布线掩模使绝缘层部分刻蚀到相应于所要的金属布线的厚度，从而形成一槽，然后在槽底部进行硅离子注入，从而形成硅注入区；除去金属布线掩模，然后在槽中选择性地生长钨，从而形成第一选择性生长钨层；在第一钨层形成后获得的结构上形成接触掩膜，然后用接触掩模对第一钨层和绝缘层进行刻蚀，从而形成暴露第一导电层的接触孔；除去接触掩模，然后在接触孔中选择性地生长钨，从而形成填满接触孔的第二选择性生长钨层，这里用作上导电层的第一钨层与第一导电层电气相连。
依据另一方面，本发明提供了用于形成半导体器件金属布线的方法，此半导体器件包括：设有扩散区和元件隔离层的半导体衬底；在半导体衬底上形成的第一导电层；在第一导电层形成后获得的结构上形成的第一绝缘层，此第一绝缘层具有平面形表面；多个彼此间隔的第二导电层；第一绝缘层形成后获得的结构上的第二绝缘导层；以及与扩散区和第二导电层在电气上相连的金属布线，此方法包括下述步骤：用金属布线掩模把第二导电层部分刻蚀到所要的金属布线的厚度，从而形成槽，然后在槽底部进行硅离子注入，从而形成硅注入区；在槽中选择性地生长钨，从而形成第一选择性生长钨层；用接触掩模对第一选择性生长钨层、第二绝缘层和第一绝缘层进行刻蚀，从而分别形成用于暴露第二导电层和扩散区的接触孔；在接触孔中选择性地生长钨，从而分别形成填充接触孔的第二选择性生长钨层，这里每个第一钨层与每个相应的扩散区和每个相应的第二导电层在电气上相连。
通过以下参考附图对实施例的描述将使本发明的其它目的和方面变得很明显，其中：
图1A到1C是分别示出用于形成半导体器件金属布线的通常方法的剖面图；
图2A到2E是分别示出依据本发明第一个实施例用于形成半导体器件金属布线的方法的连续步骤的剖面图；
图3A到3F是分别示出依据本发明第二个实施例用于形成半导体器件金属布线的方法的连续步骤的剖面图。
图2A到2E是分别示出依据本发明的第一个实施例用于形成半导体器件金属布线的方法的连续步骤的剖面图。
依据本发明的此实施例，备有如图2A所示的已确定扩散区2的半导体衬底11。在半导体衬底11上形成绝缘层13。
然后，如图2B所示，在绝缘层13上形成金属布线掩模14。用此金属布线掩模14，把绝缘层13的所要的区域刻蚀到相应于所要的金属布线厚度的厚度，从而形成纵向延伸的槽15。
如图2C所示，然后将硅离子注入槽15的底部，从而形成将在随后淀积钨的步骤中用作反应源的硅注入区20。然后，除去金属布线掩模14。接着在槽15中生长钨层16。为了增加钨的生长速率，可另外将磷(P)、硼(B)或砷(As)注入硅注入区20。
如图2D所示，接着在此结构上形成接触掩模17。用此接触掩模17，对选择性生长钨层16和绝缘层13相应于接触孔区的部分进行部分刻蚀，从而形成一接触孔18，通过该孔将扩散区12暴露出来。
如图2E所示，当接触孔18形成后，除去接触掩模17。接着，在接触孔18中选择性生长另一钨层19从而接触孔18完全由钨填满，以使上导电层(即，选择性生长钨层16)与下扩散区12在电气上相连。应该注意，因为钨层19的生长速率高于钨层16的生成速率，所以在填充接触孔18期间不形成空隙。
图3A至3F示出依据本发明的第二个实施例用于形成半导体器件金属布线的方法的连续步骤。
依据本发明的此实施例，如图3A所示，备有其中有彼此间隔的元件隔离层22。在相邻元件隔离层22之间，形成了扩散区23。可能由多晶硅层构成的第一导电层24与每个元件隔离层22交叠。在此结构上，形成了第一绝缘层25。在第一绝缘层25上形成多个互相间隔的第二导电层26，每个都由例如多晶硅层等构成。然后在此结构上形成第二绝缘层27。在实施以上步骤的过程中，在元件区上形成元件。完成这个步骤后，在第二绝缘层27上形成了金属布线掩模28。
用此金属布线掩模28，把第二绝缘层27的所要的区域刻蚀到相应于所要的金属布线厚度的厚度，从而如图3B所示形成槽35。然后将硅离子注入每个槽35底部，从而形成在随后淀积钨的步骤中用作反应源的硅注入区29。然后，除去金属布线掩模28。为了增加钨的生长速率，可另外将磷、硼或砷等注入硅注入区29中。
然后，如图3C所示，在每个槽35中选择性地生长钨层30。此钨层30将用作上导电层。因为钨层30生长在槽35中，即使不实施单独的平面化，在涉及二层、三层或多层金属处理的半导体器件的制造中也能获得平面化的效果。
如图3D所示，在此结构中，然后形成了接触掩模31，从而暴露出选择性生长钨层30。
如图3E所示，用此接触掩模，对选择性生长钨层30和第二绝缘层27相应于接触孔区的部分进行部分刻蚀，从而形成接触孔32，通过该孔暴露出相应的第二导电层26。随后，对第一绝缘层25的暴露部分进行刻蚀，从而形成接触孔32′，通过该孔暴露出扩散区23。
如图3F所示，然后在接触孔32和和32′中选择性地生长各自的钨层33从而使它们与扩散区23或第二层电层26在电气上相连。这样，依据最深的接触孔32′实施生长钨。相应地，钨在接触孔32中过生长。应该注意因为扩散区23或第二导电层26上的钨层33的生长速率高于用作金属布线的钨层30的生长速率，所以在填充接触孔32和32′期间不形成空隙。
从以上的描述很明显看出，本发明提供了一种用于形成半导体器件金属布线的方法，它能防止在由于下层拓扑在产生图形过程中留下残留物质及防止在接触孔中产生空隙。相应地，可防止金属布线短路或断开。
虽然为说明的目的揭示了本发明的较佳实施例，本领域中技术人员能知道在不背离所附的权利要求中揭示的本发明的范围和精神的情况下，也可能有不同变化，增添和替换。

Claims (10)

1.一种用于形成半导体器件金属布线的方法，包括下列步骤：
在半导体衬底上形成第一导电层；
在第一导电层形成后获得的结构上形成绝缘层，然后在绝缘层上形成金属布线掩模；
其特征在于所述方法还包括下列步骤：
用金属布线掩模把绝缘层部分刻蚀到相应于所要的金属布线的厚度，从而形成一槽，然后在槽底部注入硅离子，从而形成硅注入区；
除去金属布线掩模，然后在槽中选择性地生长钨，从而形成第一选择性生长钨层；
在此第一钨层形成后获得的结构上形成接触掩模，然后用接触掩模对第一钨层和绝缘层进行刻蚀，从而形成用来暴露出第一导电层的接触孔；以及
除去接触掩模，然后在接触孔中选择性地生长钨，从而形成填满接触孔的第二选择性生长钨层，这里用作上导电层的第一钨层与第一导电层在电气上相连。
2.如权利要求1所述的方法，其特征在于第一导电层是一扩散区。
3.如权利要求1所述的方法，其特征在于槽的深度相应于金属布线的厚度。
4.如权利要求1所述的方法，其特征在于还包括在槽底部形成的硅注入区上另外注入磷、硼或砷的步骤。
5.如权利要求1所述的方法，其特征在于第二选择性生长钨层生长在第一导电层上。
6.一种用于形成半导体器件金属布线的方法，其中半导体器件包括设有扩散区和元件隔离层的半导体衬底；在半导体衬底上形成的第一导电层；在第一导电层形成后获得的结构上形成的第一绝缘层；多个彼此间隔的第二导电层；在第一绝缘层形成后获得的结构上形成的第二绝缘层；以及与扩散区和第二导电层接触的金属布线，其特征在于所述方法包括以下步骤：
用一金属布线掩模把第二绝缘层部分刻蚀到所要的金属布线的厚度，从而形成槽，然后在各个槽底部注入硅离子，从而形成硅注入区；
在槽中选择性地生长钨，从而形成第一选择性生长钨层；
用一接触掩模刻蚀第一选择性生长钨层、第二绝缘层和第一绝缘层，从而分别形成用来暴露出第二导电层和扩散区的接触孔；
在接触孔中选择性地生长钨，从而分别形成填充接触孔的第二选择性生长钨层，这里每个第一钨层与每个相应的扩散区和每个相应的第二导电层在电气上相连。
7.如权利要求6所述的方法，其特征在于在具有不同深度的接触孔中选择性地生长钨的步骤参照最深的接触孔来实施。
8.如权利要求6所述的方法，其特征在于槽的深度相应于金属布线的厚度。
9.如权利要求6所述的方法，其特征在于此方法还包括分别在槽底部形成的硅注入区中另外注入磷、硼或砷的步骤。
10.如权利要求6所述的方法，其特征在于第二选择性生长钨层生长在扩散区上。
CN95118735A 1994-10-12 1995-10-12 用于形成半导体器件金属布线的方法 Expired - Fee Related CN1074857C (zh)

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