KR960019589A - 도전선 형성방법 - Google Patents

도전선 형성방법 Download PDF

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KR960019589A
KR960019589A KR1019940032131A KR19940032131A KR960019589A KR 960019589 A KR960019589 A KR 960019589A KR 1019940032131 A KR1019940032131 A KR 1019940032131A KR 19940032131 A KR19940032131 A KR 19940032131A KR 960019589 A KR960019589 A KR 960019589A
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forming
conductive material
trench
conductive
conductive line
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KR1019940032131A
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KR0138295B1 (ko
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최지현
신홍재
황병근
정우인
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김광호
삼성전자 주식회사
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Priority to US08/557,534 priority patent/US5629238A/en
Priority to JP31056595A priority patent/JP3504408B2/ja
Publication of KR960019589A publication Critical patent/KR960019589A/ko
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Publication of KR0138295B1 publication Critical patent/KR0138295B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

플루오린이 도우프된 산화막을 도전선과 도전선 사이의 절연막으로 사용하는 도전선 형성방법에 대해 기재되어 있다. 이는, 하부구조물 상에 플루오린이 도우프된 산화막을 형성하는 제1공정, 도전성이 형성될 영역의 상기 산화막을 식각하여 트렌치를 형성하는 제2공정, 결과물 전표면에 절연층을 형성하는 제3공정, 결과물 상에 도전물질을 증착하는 제4공정, 및 상기 도전물질을 에치백하여 상기 트렌치에만 도전물질이 남도록 함으로써 상기 도전선을 형성하는 제5공정을 포함하는 것을 특징으로 한다. 도전선은 알루미늄이 함유된 물질로 구성되고, 절연층은 이상화실리콘으로 구성된다. 따라서 SiOF막과 알루미늄이 함유된 도전선 사이에 절연막을 개재함으로써 도전선의 부식을 방지하였다.

Description

도전선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3A도 내지 제3C도는 본 발명의 제1실시예의 방법에 의한 도전선 형성방법을 설명하기 위해 도시된 단면도들이다,
제4도는 본 발명의 제2실시예의 방법에 의해 형성된 도전선을 도시한 단면도이다,
제5A도 내지 제5C도는 본 발명의 제3실시예의 방법에 의한 도전선 형성방법을 설명하기 위해 도시된 단면도들이다.

Claims (12)

  1. 하부구조물 상에 플루오린이 도우프된 산화막을 형성하는 제1공정; 도전성이 형성될 영역의 상기 산화막을 식각하여 트렌치를 형성하는 제2공정; 결과물 전표면에 절연층을 형성하는 제3공정; 결과물 상에 도전물질을 증착하는 제4공정; 및 상기 도전물질을 에치백하여 상기 트렌치에만 도전물질이 남도록 함으로써 상기 도전선을 형성하는 제5공정을 포함하는 것을 특징으로 하는 도전선 형성방법.
  2. 제1항에 있어서, 상기 에치백은 화학ㆍ물리적 폴리슁(Chemical Mechnical Polishing)으로 진행되는 것을 특징으로 하는 도전선 형성방법.
  3. 제1항에 있어서, 상기 제3공정 이후에, 상기 절연층을 이방성식각함으로써 상기 트렌치의 측벽에 스페이서를 형성하는 공정을 더 포함하는 것을 특징으로 하는 도전선 형성방법.
  4. 제1항에 있어서, 상기 하부구조물은 하부 도전선 또는 반도체기판 상에 절연물질층이 형성되어 있는 구조물인 것을 특징으로 하는 도전선 형성방법.
  5. 제4항에 있어서, 상기 제3공정 이후에, 트렌치 하부에 있는 상기 절연물질층을 부분적으로 식각하여 상기 하부 도전선 또는 반도체기판을 표면으로 노출시키는 공정을 더 포함하는 것을 특징으로 하는 도전선 형성방법.
  6. 제1항에 있어서, 상기 도전물질은 상기 플루오린이 도우프된 산화막과 반응하여 부식을 일으키는 물질인 것을 특징으로 하는 도전선 형성방법.
  7. 제6항에 있어서, 상기 도전물질은 알루미늄인 것을 특징으로 하는 도전선 형성방법.
  8. 제1항에 있어서, 상기 절연층은 이산화실리콘 또는 보론과 인이 도우프된 실리콘 글래스(Boro-Phosphorus Silicate Glass)인 것을 특징으로 하는 도전선 형성방법.
  9. 하부 도전선 또는 반도체기판 상에 절연물질층을 형성하는 제1공정; 상기 하부 도전선 또는 반도체기판을 표면으로 노출시키는 콘택홀을 형성하는 제2공정; 결과물 전면에 제1도전물질을 증착하는 제3공정; 상기 제1도전물질을 에치백하여 상기 콘택홀을 채우는 플러그층을 형성하는 제4공정; 결과물 전면에 플루오린이 도우프된 산화막을 형성하는 제5공정; 상기 플러그층이 표면으로 완전히 노출되도록 상기 산화막을 식각하여 트렌치를형성하는 제6공정; 결과물 전표면에 절연층을 형성하는 제7공정; 상기 절연층을 이방성식각하여 상기 트렌치의 측벽에 스페이서를 형성하는 제8공정; 결과물 상에 제2도전물질을 증착하는 제9공정; 및 상기 제2도전물질을 에치백하여 상기 트렌치에만 제2도전물질이 남도록 함으로써 상기 도전선을 형성하는 제10공정을 포함하는 것을 특징으로 하는 도전선 형성방법.
  10. 제9항에 있어서, 상기 제1도전물질은 텅스텐, 알루미늄, 텅스텐 나이트라이드, 티타늄 또는 티타늄 나이트라이드등의 물질인 것을 특징으로 하는 도전선 형성방법.
  11. 제9항에 있어서, 상기 제2도전물질은 상기 산화막과 반응하여 부식을 일으키는 물질인 것을 특징으로 하는 도전선 형성방법.
  12. 제11항에 있어서, 상기 제2도전물질은 알루미늄인 것을 특징으로 하는 도전선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940032131A 1994-11-30 1994-11-30 도전선 형성방법 KR0138295B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940032131A KR0138295B1 (ko) 1994-11-30 1994-11-30 도전선 형성방법
US08/557,534 US5629238A (en) 1994-11-30 1995-11-14 Method for forming conductive line of semiconductor device
JP31056595A JP3504408B2 (ja) 1994-11-30 1995-11-29 半導体素子の導電線の形成方法

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Application Number Priority Date Filing Date Title
KR1019940032131A KR0138295B1 (ko) 1994-11-30 1994-11-30 도전선 형성방법

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KR960019589A true KR960019589A (ko) 1996-06-17
KR0138295B1 KR0138295B1 (ko) 1998-06-01

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KR100700255B1 (ko) * 1998-12-18 2007-03-26 로무 가부시키가이샤 반도체장치의 제조방법

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US5629238A (en) 1997-05-13
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