KR960019549A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

Info

Publication number
KR960019549A
KR960019549A KR1019950041786A KR19950041786A KR960019549A KR 960019549 A KR960019549 A KR 960019549A KR 1019950041786 A KR1019950041786 A KR 1019950041786A KR 19950041786 A KR19950041786 A KR 19950041786A KR 960019549 A KR960019549 A KR 960019549A
Authority
KR
South Korea
Prior art keywords
photosensitive resin
thickness
semiconductor device
manufacturing
cavity
Prior art date
Application number
KR1019950041786A
Other languages
English (en)
Other versions
KR100204694B1 (ko
Inventor
마사하루 시라이
겐지 데라다
유타카 즈카다
슈헤이 즈치타
Original Assignee
윌리암 티. 엘리스
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윌리암 티. 엘리스, 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 윌리암 티. 엘리스
Publication of KR960019549A publication Critical patent/KR960019549A/ko
Application granted granted Critical
Publication of KR100204694B1 publication Critical patent/KR100204694B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

바이어 홈에 대한 도체층의 부착을 용이하게, 또한 균일하게 실행하기 위한 바이어 홀을 거의 주발형 형상으로 하는데에 바람직한 반도체 장치의 제조방법을 제공한다.
감광성 수지(3)를 최종적으로 절연층으로써 필요한 두께에 대하여 후 공정의 감광성 수지(3)의 연삭에 의해 제거되는 두께를 가한 두께로 되도록 기판(1)위에 설치한다. 이어서 감광성 수지(3)에 노광ㆍ현상ㆍ에칭에 의해 소정의 패턴으로 공동을 형성하며, 공동(8)이 형성된 감광성 수지(3)를 열 경화한다. 그후 도면에서 파선으로 도시하는 광 경화층(6a)과 열 경화층(3a)의 일부를 연삭제거하면, 거의 주발형 형상의 바이어 홀(9)이 형성된다.

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명 반도체 장치의 제조방법에 있어서의 감광성 수지층의 성형 공정을 도시한 단면도.

Claims (3)

  1. 감광성 수지를 포함하는 1개 이상 종류의 수지로 이루어지며, 상기 감광성 수지가 최상부에 위치하며, 제1두께 이상의 두께를 갖는 수지층을 기판위에 형성하는 공정과, 상기 수지층을 노광ㆍ현상ㆍ에칭하여 원하는 패턴으로 공동을 형성하는 공정과, 상기 공동을 형성한 수지층을 열 경화시키는 공정과, 상기 열 경화시킨 수지층의 일부를 상기 제1두께로 될때까지 연삭제어하며, 상기 공동의 일부로 구성되는 바이어 홀(via hole)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  2. 제1항에 있어서, 상기 에칭은 상기 수지층의 두께 방향에 직교에 가까운 방향으로 에칭이 이루어지는 공정을 특징으로 하는 반도체 장치의 제조방법.
  3. 제1항에 있어서, 상기 바이어 홀은 그 개구부의 면적이 바닥부의 면적보다도 크게되는 공정을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950041786A 1994-11-22 1995-11-17 유기물 칩 캐리어의 제조방법 KR100204694B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6288114A JP2571677B2 (ja) 1994-11-22 1994-11-22 半導体装置の製造方法
JP94-288114 1994-11-22

Publications (2)

Publication Number Publication Date
KR960019549A true KR960019549A (ko) 1996-06-17
KR100204694B1 KR100204694B1 (ko) 1999-06-15

Family

ID=17725989

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950041786A KR100204694B1 (ko) 1994-11-22 1995-11-17 유기물 칩 캐리어의 제조방법

Country Status (3)

Country Link
US (1) US5784781A (ko)
JP (1) JP2571677B2 (ko)
KR (1) KR100204694B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3398557B2 (ja) * 1997-01-29 2003-04-21 インターナショナル・ビジネス・マシーンズ・コーポレーション 表層配線プリント基板の製造方法
US6005198A (en) * 1997-10-07 1999-12-21 Dimensional Circuits Corporation Wiring board constructions and methods of making same
KR100577784B1 (ko) * 1999-06-25 2006-05-10 비오이 하이디스 테크놀로지 주식회사 박막 트랜지스터 액정 표시소자의 제조방법
US6569604B1 (en) * 1999-06-30 2003-05-27 International Business Machines Corporation Blind via formation in a photoimageable dielectric material
US20080213991A1 (en) * 2007-03-02 2008-09-04 Airdio Wireless Inc. Method of forming plugs
JP6779697B2 (ja) * 2016-07-29 2020-11-04 株式会社ジャパンディスプレイ 電子機器及びその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2773366B2 (ja) * 1990-03-19 1998-07-09 富士通株式会社 多層配線基板の形成方法
JPH0636472B2 (ja) * 1990-05-28 1994-05-11 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 多層配線基板の製造方法
JPH04181749A (ja) * 1990-11-16 1992-06-29 Sumitomo Metal Mining Co Ltd ２層ｔａｂ製造用フォトマスク
JPH0752744B2 (ja) * 1991-04-04 1995-06-05 チッソ株式会社 リ−ド強度のすぐれたフィルムキャリアの製造方法
JP2920854B2 (ja) * 1991-08-01 1999-07-19 富士通株式会社 ビィアホール構造及びその形成方法
JPH06314869A (ja) * 1993-04-30 1994-11-08 Eastern:Kk プリント配線板のスルーホール形成方法

Also Published As

Publication number Publication date
JPH08148566A (ja) 1996-06-07
US5784781A (en) 1998-07-28
KR100204694B1 (ko) 1999-06-15
JP2571677B2 (ja) 1997-01-16

Similar Documents

Publication Publication Date Title
KR930001443A (ko) 마이크로렌즈 형성방법
KR920005304A (ko) 반도체집적회로장치의 배선접속구조 및 그 제조방법
US4536249A (en) Integrated circuit processing methods
KR960019549A (ko) 반도체 장치의 제조방법
KR900003977A (ko) 반도체장치의 제조방법
TW399298B (en) Manufacturing method of via hole
JPH0483391A (ja) モールド成形回路基板の製造方法
ATE135495T1 (de) Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht
KR950021063A (ko) 반도체 소자의 스텝 커버리지(Step coverage) 향상방법
KR100418904B1 (ko) 광도파로 제조 방법
KR960014056B1 (ko) 감광막 패턴 형성방법
KR0142837B1 (ko) 반도체소자의 미세패턴 형성방법
JP2005353922A (ja) 電子部品の製造方法
KR970053546A (ko) 반도체 장치의 금속 배선 형성 방법
JPH07106753A (ja) 印刷配線板の製造方法
KR960026231A (ko) 텅스텐 플러그 제조방법
JPH0237756A (ja) 放熱板付半導体装置
KR970053427A (ko) 트렌치 소자분리 영역을 갖는 반도체장치의 마스크 정렬키 형성방법
KR910008801A (ko) 반도체장치의 제조방법
KR950021050A (ko) 웨이퍼의 단차 완화 방법
JPH06334303A (ja) 薄膜混成集積回路の製造におけるフォトレジスト層の形成方法
KR970003482A (ko) 반도체 소자의 콘택홀 형성방법
KR960006029A (ko) 반도체소자의 트랜치 제조방법
KR960001881A (ko) 반도체소자의 미세 도전층 패턴 제조방법
JPH0818197A (ja) モールド成形回路基板の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110201

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee