KR900003977A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR900003977A
KR900003977A KR1019880010249A KR880010249A KR900003977A KR 900003977 A KR900003977 A KR 900003977A KR 1019880010249 A KR1019880010249 A KR 1019880010249A KR 880010249 A KR880010249 A KR 880010249A KR 900003977 A KR900003977 A KR 900003977A
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KR
South Korea
Prior art keywords
photosensitive resin
contact hole
semiconductor device
manufacturing
insulating film
Prior art date
Application number
KR1019880010249A
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English (en)
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KR920004538B1 (ko
Inventor
이철진
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019880010249A priority Critical patent/KR920004538B1/ko
Priority to US07/378,660 priority patent/US4990467A/en
Priority to JP1190382A priority patent/JPH0281426A/ja
Publication of KR900003977A publication Critical patent/KR900003977A/ko
Application granted granted Critical
Publication of KR920004538B1 publication Critical patent/KR920004538B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 3도는 본 발며의 한 실시예에 따른 반도체장ㅊ치의 제조공정도.
제 4 도는 본 발명의 다른 실시예에 따른 반도체장치의 제조공정도.

Claims (5)

  1. 기판(1)에 불순물을 주입시켜 불순물 주입영역(2)을 형성하고 절연막(3)을 도포, 식각시켜 콘택홀을 형성한 다음 텅스텐막(4)을 콘택홀에 선택적으로 도포시키는 반도체장치의 제조방법에 있어서, 절연막(3)위에 감광성수지를 도포시켜 감광성 수지를 마스크로 이용하여 콘택홀을 형성하며, 콘택홀에 텅스텐막(4)을 선택적으로 도포시켜 콘택홀 내부에만 텅스텐막(4)이 존재하도록 하는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제 1 항에 있어서, 절연막(3)에 감광성수지(6)를 도포시켜 감광성수지에 패턴을 형성하고, 감광성수지(6)를 마스크로 하여 절연막(3)을 식각하여 콘택홀을 형성하며, 콘택홀에 텅스텐막(4)을 선택적으로 도포시키고, 감광성수지(6) 제거시 감광성수지(6)위에 도포된 텅스텐잔유물(5)을 동시에 제거하여 콘택홀 내부에만 텅스텐막(4)을 도포시키는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제 1항에 있어서, 절연막(3)위에 제 1감광성수지(7)와 제 2감광성수지(8)를 연속적으로 도포하고, 제 2감광성수지(8)를 사진식각공정을 통해 식각하여 제 2감광성수지(8)에 패턴을 형성하며, 제 2감광성수지(8)를 마스크로 하여 제 1 감광성수지(7)에 패턴을 형성한 다음 제 2감광성수지(8)를 제거하고, 제 1감광성수지97)를 마스크로 하여 절연막(3)을 식각하여 콘택홀으 형성하며, 콘택홀에 텅스텐막(4)을 선택적으로 도포시킨 다음 제 1감광성수지(70를 제거하여 콘택홀 내부에만 텅스텐막(4)을 도포시키는 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제 3 항에 있어서, 제 1감광성수지(7)로 고온에서 잘견디는 폴리이미드나 PMGI를 사용하고 제 2감광성수지98)로 저온에서 사용하는 포지티브포토리지트를 사용하여 감광성수지를 2층막으로 구성하는 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제 3 항에 있어서, 제 1감광성수지(7)를 RIE 견식식각하고 제 2감광성수지(80를 습식식각시켜 제 1 및 제 2감광성수지(7,8)에 패턴을 형성하는 것을 특징으로 하는 반도체장치의 제조방법.
    ※참고사항: 최초출원 내용에 의하여 공개하는 것임.
KR1019880010249A 1988-08-11 1988-08-11 반도체장치의 제조방법 KR920004538B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019880010249A KR920004538B1 (ko) 1988-08-11 1988-08-11 반도체장치의 제조방법
US07/378,660 US4990467A (en) 1988-08-11 1989-07-12 Method of preventing residue on an insulator layer in the fabrication of a semiconductor device
JP1190382A JPH0281426A (ja) 1988-08-11 1989-07-20 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880010249A KR920004538B1 (ko) 1988-08-11 1988-08-11 반도체장치의 제조방법

Publications (2)

Publication Number Publication Date
KR900003977A true KR900003977A (ko) 1990-03-27
KR920004538B1 KR920004538B1 (ko) 1992-06-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880010249A KR920004538B1 (ko) 1988-08-11 1988-08-11 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US4990467A (ko)
JP (1) JPH0281426A (ko)
KR (1) KR920004538B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190136234A (ko) * 2018-05-30 2019-12-10 엘에스산전 주식회사 엘리베이터 시스템의 브레이크 제어방법

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8907898D0 (en) 1989-04-07 1989-05-24 Inmos Ltd Semiconductor devices and fabrication thereof
US5185278A (en) * 1990-10-22 1993-02-09 Motorola, Inc. Method of making self-aligned gate providing improved breakdown voltage
US5200360A (en) * 1991-11-12 1993-04-06 Hewlett-Packard Company Method for reducing selectivity loss in selective tungsten deposition
JP2885616B2 (ja) * 1992-07-31 1999-04-26 株式会社東芝 半導体装置およびその製造方法
US5420076A (en) * 1994-01-03 1995-05-30 Texas Instruments Incorporated Method of forming a contact for multi-level interconnects in an integrated circuit
US5786273A (en) * 1995-02-15 1998-07-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device and associated fabrication method
TW359016B (en) * 1996-04-29 1999-05-21 Applied Materials Inc Selective aluminum chemical vapor deposition via fill using a sacrificial layer

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DE210372C (ko) *
GB1053069A (ko) * 1963-06-28
JPS5259580A (en) * 1975-11-11 1977-05-17 Matsushita Electric Ind Co Ltd Photo etching method
JPS5923475B2 (ja) * 1978-12-07 1984-06-02 松下電子工業株式会社 半導体装置用電極の形成方法
JPS5749230A (en) * 1980-09-08 1982-03-23 Matsushita Electronics Corp Forming method for electrode
JPS5792849A (en) * 1980-12-01 1982-06-09 Mitsubishi Electric Corp Manufacture of semiconductor device
US4440804A (en) * 1982-08-02 1984-04-03 Fairchild Camera & Instrument Corporation Lift-off process for fabricating self-aligned contacts
US4532702A (en) * 1983-11-04 1985-08-06 Westinghouse Electric Corp. Method of forming conductive interconnection between vertically spaced levels in VLSI devices
JPH0670983B2 (ja) * 1985-08-19 1994-09-07 富士通株式会社 化学気相成長方法
US4824802A (en) * 1986-02-28 1989-04-25 General Electric Company Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190136234A (ko) * 2018-05-30 2019-12-10 엘에스산전 주식회사 엘리베이터 시스템의 브레이크 제어방법

Also Published As

Publication number Publication date
KR920004538B1 (ko) 1992-06-08
US4990467A (en) 1991-02-05
JPH0281426A (ja) 1990-03-22

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