KR950007051A - 얼라이먼트 마크 배치방법 - Google Patents

얼라이먼트 마크 배치방법 Download PDF

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KR950007051A
KR950007051A KR1019940017521A KR19940017521A KR950007051A KR 950007051 A KR950007051 A KR 950007051A KR 1019940017521 A KR1019940017521 A KR 1019940017521A KR 19940017521 A KR19940017521 A KR 19940017521A KR 950007051 A KR950007051 A KR 950007051A
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alignment mark
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alignment
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노리오 모리야마
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가나미야지 준
오끼뎅끼 고오교오 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01—Chemical elements
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

하나의 웨이퍼상에 형성할 수 있는 반도체장치의 수를 감하지 않고, 스크라이브 라인을 실효적으로 넓힐 수가 있는 얼라이먼트 마크 배치방법을 제공한다.
스크라이브 라인(3)의 얼라이먼트 마크(4a, 4b)가 형성되는 위치에 대응하고 있는 영역부분(11a, 11b)의 폭만을 얼라이먼트 마크(4a, 4b)의 폭보다도 크게 형성하고, 그 크게 형성한 영역부분(11a, 11b)내에 얼라이먼트 마크(4a)를 설치하는 동시에, 사용하여 불요하게 된 얼라이먼트 마크(4a)가 출현할때마다 불효하게 된 얼라이먼트 마크(4a)에 대응하고 있는 영역부분(11a)의 일부와 얼라이먼트 마크(4a)의 일부(4c)를 새로운 스크라이브 라인(9)로 덮어서 영역부분(11a)를 통상의 스크라이브 라인(3)의 폭으로 되돌리면서 아직 얼라이먼트 마크가 형성되어 있지 않은 타의 전기 영역부분(11b)에 새로운 얼라이먼트 마크(4a)를 형성하도록 했다.

Description

얼라이먼트 마크 배치방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예를 설명하기 위한 웨이퍼의 요부구조도.
제2도는 본 발명의 얼라이먼트 마크 배치 수순을 설명하기 위한 도면.
제3도는 본 발명의 얼라이먼트 마크 배치수순을 설명하기 위한 도면.

Claims (1)

  1. 웨이퍼상에 형성된 복수의 반도체장치를 개개로 분할하기 위한 스크라이브 라인상에 틀리는 공정으로 사용되는 얼라이먼트 마크를 복수개, 상기 스크라이브 라인 폭보다도 큰폭으로 형성하여 배치하는 방법에 있어서, 상기 스크라이브 라인의 상기 얼라이먼트 마크가 형성되는 위치에 대응하고 있는 영역의 폭만을 상기 얼라이먼트 마크의 폭보다 크게 형성하고, 그 크게 형성한 영역부분내에 상기 얼라이먼트 마크를 설치하는 동시에, 사용하여 불요하게된 상기 얼라이먼트 마크가 출현할때마다 상기 불요하게 딘 얼라이먼트 마크에 대응하고 있는 영역부분의 일부와, 이 영역부분내에 형성되어 있는 상기 얼라이먼트 마크의 일부를 새로운 스크라이브 라인으로 덮어서 상기 영역부분을 상기 통상의 스크라이브 라인의 폭으로 되돌리면서 아직 얼라이먼트 마크가 형성되어 있지 않은 타의 상기 영역부분내에 새로운 얼라이먼트 마크를 형성하도록 배치하는 것을 특징으로 하는 얼라이먼트 마크 배치방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940017521A 1993-08-26 1994-07-20 얼라인먼트 마크의 배치방법 KR100272056B1 (ko)

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Application Number Priority Date Filing Date Title
JP93-234144 1993-08-26
JP23414493A JP2790416B2 (ja) 1993-08-26 1993-08-26 アライメントマーク配置方法

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KR950007051A true KR950007051A (ko) 1995-03-21
KR100272056B1 KR100272056B1 (ko) 2000-12-01

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US5496777A (en) 1996-03-05
US5684333A (en) 1997-11-04

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