JP6667618B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 317
- 238000004519 manufacturing process Methods 0.000 title claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 114
- 239000002184 metal Substances 0.000 claims description 114
- 238000000034 method Methods 0.000 claims description 48
- 238000010030 laminating Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 224
- 238000005530 etching Methods 0.000 description 42
- 239000000463 material Substances 0.000 description 26
- 230000004048 modification Effects 0.000 description 14
- 238000012986 modification Methods 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 14
- 239000004020 conductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Description
図1は、本発明の第1の実施形態の半導体装置10の構成を示している。半導体装置10は、積層型の半導体装置である。積層型の半導体装置は、裏面照射型撮像装置でありうる。図1において、半導体装置10の断面が示されている。
図24は、本発明の第1の実施形態の第1の変形例の半導体装置11の構成を示している。図24において、半導体装置11の断面が示されている。図24に関して、図1と異なる点を説明する。
図31は、第1の実施形態の第2の変形例の半導体装置12の構成を示している。図31において、半導体装置12の断面が示されている。図31に関して、図1と異なる点を説明する。
図32は、本発明の第2の実施形態の半導体装置13の構成を示している。図32において、半導体装置13の断面が示されている。図32に関して、図31と異なる点を説明する。
100 第1の半導体層
110 第1のパッド
120,121,122 第2のパッド
130 第1の開口部
140 第2の開口部
150,151,152 アライメントマーク
160 金属膜
200 第2の半導体層
210 第3の開口部
220 第4の開口部
Claims (7)
- 第1の主面を有し、かつ第1の開口部および第2の開口部が前記第1の主面に形成された第1の半導体層と、
第2の主面を有し、かつ前記第1の半導体層に積層され、かつ第3の開口部および第4の開口部が形成された第2の半導体層と、
ワイヤボンディングのための第3の主面を有し、かつ前記第3の主面は前記第1の開口部に配置された第1のパッドと、
アライメントマークが形成された第4の主面を有し、かつ前記第4の主面は前記第2の開口部に配置された第2のパッドと、
を有し、
前記第2の主面は前記第1の主面と対向し、
前記第3の開口部および前記第4の開口部は、前記第2の半導体層を貫通し、
前記第1の開口部は、前記第3の開口部と重なり、
前記第2の開口部は、前記第4の開口部と重なり、
第1の方向に垂直な第2の方向における前記第1のパッドの幅は、前記第2の方向における前記第1の開口部の幅よりも大きく、
前記第2の方向における前記第2のパッドの幅は、前記第2の方向における前記第2の開口部の幅よりも大きく、
前記第1の方向は前記第1の半導体層の厚さ方向である
半導体装置。 - 前記第1のパッドおよび前記第2のパッドは、同一の金属で構成され、
前記アライメントマークは、前記第4の主面に形成された凹部である
請求項1に記載の半導体装置。 - 前記第1のパッドおよび前記第2のパッドは、同一の金属で構成され、
前記アライメントマークは、前記第4の主面に形成された凸部である
請求項1に記載の半導体装置。 - 前記第1のパッドおよび前記第2のパッドは、同一の金属で構成され、
前記アライメントマークは、前記第2のパッドに形成された貫通孔である
請求項1に記載の半導体装置。 - 金属膜をさらに有し、
前記第2のパッドは、前記第2の半導体層と前記金属膜との間に配置されている
請求項4に記載の半導体装置。 - 第1の半導体層を第2の半導体層に積層する工程であって、前記第1の半導体層は第1の主面を有し、前記第2の半導体層は第2の主面を有し、かつ前記第2の主面は前記第1の主面と対向する第1の工程と、
第1のパッドおよび第2のパッドを前記第1の半導体層に形成する工程であって、前記第1のパッドは、ワイヤボンディングのための第3の主面を有し、前記第2のパッドは、アライメントマークが形成された第4の主面を有する第2の工程と、
第3の開口部および第4の開口部を前記第2の半導体層に形成する工程であって、前記第3の開口部および前記第4の開口部は、前記第2の半導体層を貫通する第3の工程と、
第1の開口部および第2の開口部を前記第1の半導体層の前記第1の主面に形成する工程であって、前記第1の開口部は、前記第3の開口部と重なり、前記第2の開口部は、前記第4の開口部と重なり、前記第3の主面は前記第1の開口部に配置され、前記第4の主面は前記第2の開口部に配置される第4の工程と、
を有する半導体装置の製造方法。 - 金属膜を前記第1の半導体層に形成する第5の工程をさらに有し、
前記第1のパッドおよび前記第2のパッドは、同一の金属で構成され、
前記アライメントマークは、前記第2のパッドに形成された貫通孔であり、
前記第2のパッドは、前記第2の半導体層と前記金属膜との間に配置されている
請求項6に記載の半導体装置の製造方法。
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PCT/JP2016/061900 WO2017179152A1 (ja) | 2016-04-13 | 2016-04-13 | 半導体装置および半導体装置の製造方法 |
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JP2652015B2 (ja) * | 1987-04-07 | 1997-09-10 | セイコーエプソン株式会社 | 半導体装置 |
JPH0695517B2 (ja) * | 1987-06-25 | 1994-11-24 | 日本電気株式会社 | 半導体装置 |
JPH04239736A (ja) | 1991-01-23 | 1992-08-27 | Nec Corp | 半導体装置の電極構造 |
JPH06232205A (ja) * | 1992-12-11 | 1994-08-19 | Fujitsu Ltd | 半導体装置の実装方法と半導体装置 |
JP2790416B2 (ja) * | 1993-08-26 | 1998-08-27 | 沖電気工業株式会社 | アライメントマーク配置方法 |
JP3243913B2 (ja) | 1993-11-04 | 2002-01-07 | ソニー株式会社 | 半導体装置のダミーパッド構造 |
US5401691A (en) * | 1994-07-01 | 1995-03-28 | Cypress Semiconductor Corporation | Method of fabrication an inverse open frame alignment mark |
TW311273B (en) * | 1996-09-26 | 1997-07-21 | Holtek Microelectronics Inc | Manufacturing method of high step alignment mark |
JP4352579B2 (ja) * | 2000-05-16 | 2009-10-28 | 沖電気工業株式会社 | 半導体チップ及びその製造方法 |
WO2006118019A1 (ja) | 2005-04-28 | 2006-11-09 | Toray Engineering Co., Ltd. | 画像認識実装方法 |
JP2014082281A (ja) * | 2012-10-15 | 2014-05-08 | Olympus Corp | 基板、半導体装置、基板の製造方法 |
JP6476000B2 (ja) | 2015-02-17 | 2019-02-27 | 三菱電機株式会社 | 半導体装置および半導体モジュール |
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