CN101110388A - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

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CN101110388A
CN101110388A CNA2007101366443A CN200710136644A CN101110388A CN 101110388 A CN101110388 A CN 101110388A CN A2007101366443 A CNA2007101366443 A CN A2007101366443A CN 200710136644 A CN200710136644 A CN 200710136644A CN 101110388 A CN101110388 A CN 101110388A
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郑恩洙
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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Abstract

提供了一种用于制造半导体器件的方法。在该方法中,在半导体衬底上形成具有第一宽度的光刻胶图形,并且使用该光刻胶图形作为掩模蚀刻该半导体衬底,以形成半导体凸起部。在包括该半导体凸起部的半导体衬底的整个表面上形成氧化层。随后,除去该半导体凸起部,以形成被该氧化层包围的沟槽。之后,在该沟槽上实施覆盖蚀刻,以仅仅留下一部分形成于该沟槽周围的氧化层。在包括该部分氧化层的该半导体衬底的整个表面上沉积金属,并且除去该部分氧化层,以形成金属图形。

Description

制造半导体器件的方法
背景技术
随着半导体器件的高度集成,器件在进行着小型化。小型化半导体器件也要求线尺寸(line size)小型/减小。然而,通过现有技术的光源诸如ArF、KrF和F2光源以及光刻胶构图所实施的光刻工艺在实现金属线的微细图形方面存在局限性。
也即,由于光学系统的局限性以及光刻胶聚合物本身分辩率的局限性,导致在实现几微米的线时存在局限性。
发明内容
本发明的实施例提供一种用于制造半导体器件的方法,其能够通过氧化工艺精确地控制金属线的线宽。
在一个实施例中,一种用于制造半导体器件的方法包括:在半导体衬底上形成具有第一宽度的光刻胶图形;利用该光刻胶图形作为掩模蚀刻该半导体衬底,以形成半导体凸起部;在包括该半导体凸起部的半导体衬底的整个表面上形成氧化层;除去该半导体凸起部,以形成被该氧化层包围的沟槽;在该沟槽上实施覆盖蚀刻(blanket-etching),以仅仅保留在该沟槽周围形成的一部分氧化层;在包括该氧化层的半导体衬底的整个表面上沉积金属;以及除去该氧化层,以形成金属线。
在附图和下面的描述中将阐述一个或者多个实施例的细节。其他特征从该描述和附图以及权利要求书中显而易见。
附图说明
图1-9是根据本发明一个实施例的、用于图示制造半导体器件的方法的截面图。
图1是根据一个实施例的、在涂布了光刻胶之后的截面图。
图2是根据一个实施例的、在形成了光刻胶图形之后的截面图。
图3是根据一个实施例的、在形成了半导体凸起部之后的截面图。
图4是根据一个实施例的、在形成了氧化层之后的截面图。
图5是根据一个实施例的、在将氧化层平坦化之后的截面图。
图6是根据一个实施例的、在除去半导体凸起部之后的截面图。
图7是根据一个实施例的、在对氧化层进行覆盖蚀刻之后的截面图。
图8是根据一个实施例的、在沉积了金属之后的截面图。
图9是在按照一个实施例制造半导体器件的方法中形成了金属图形之后的器件形状的截面图。
具体实施方式
将参照附图描述依照本发明实施例的用于制造半导体器件的方法。
在对实施例的描述中,要理解,当称一层(膜)在另一层或者衬底上时,其能够直接位于另一层或者衬底上,或者也可以存在中间层。因而,当称一层是直接位于另一层或者衬底上时,就不存在中间层。
参照图1,可将光刻胶300涂布在由例如非晶硅形成的半导体衬底100上。
参照图2,通过对光刻胶300进行曝光和显影工艺,能够形成具有第一宽度d1的光刻胶图形310。这里,第一宽度d1可以是能够通过光刻工艺实现的最小线宽,并且能够以最终要形成的线的宽度作为考虑因素来确定。
参照图3,在形成具有第一线宽d1的光刻胶图形310后,能够利用该光刻胶图形310作为掩模来蚀刻半导体衬底100。
因而,如图3所示形成半导体凸起部110。半导体凸起部110具有屋脊形状并且具有同光刻胶图形310一样的第一线宽d1。
接着,参照图4,在除去光刻胶图形310后,能够在包括该半导体凸起部110的半导体衬底100的整个表面上形成氧化层200。
该氧化层200能够通过在半导体衬底100上实施湿法氧化来形成。在一个实施例中,湿法氧化是通过在大约900-1100℃的高温下注入蒸汽(H2O)一段短时间来实施的。
这里,通过该湿法氧化而形成的氧化层200的40-50%是在半导体衬底100内部形成的,而氧化层200的其余部分是在半导体衬底100的外部形成的。也即,衬底100的非晶硅产生氧化,从而氧化层形成在衬底上,一部分衬底成为氧化层200的一部分。
因此,通过产生氧化层200,半导体凸起部110成为比第一宽度d1窄的第二宽度d2。
参照图5,在形成氧化层200后,使该氧化层200平坦化,直到具有第二宽度d2的半导体凸起部110的上表面暴露出来。在一个实施例中,氧化层200能够通过化学机械抛光(CMP)工艺进行抛光。
参照图6,然后能够将通过氧化层200的平坦化而暴露的、具有第二宽度d2的半导体凸起部110除去。因此,形成了由氧化层200包围着的沟槽(trench)。该沟槽能够通过利用氟化乙烯丙烯(fluorinatedethylene propylene)(FEP)选择性地湿法蚀刻仅仅由硅形成的半导体凸起部100而形成。
也即,从半导体凸起部110的侧壁生长出的氧化层200的第一部分210以及从衬底100的上表面生长出的氧化层200的第二部分220保留下来。
随后,对保留第一部分210和第二部分220的氧化层200进行覆盖蚀刻。该蚀刻工艺能够是反应性离子蚀刻(RIE),并且直到氧化层200的第二部分220被完全除去才停止实施。
由于RIE是在垂直方向上实施的,因此第一部分210的宽度不会减小,并且第一和第二部分210和220仅仅沿高度方向被蚀刻。
也即,氧化层200的第一部分210蚀刻掉的高度是第二部分220的高度。
因此,参照图7,在该蚀刻之后还留下来的氧化层200的第一部分210与相邻的氧化层200的第一部分210相隔第二宽度d2。半导体衬底100通过彼此隔开的第一区域210之间的空间而暴露出来。
接着,参照图8,可在衬底100的整个表面上沉积金属400。金属400可包括铜。在一个实施例中,金属400的沉积可利用电子(E)束蒸发作用来实施。因此,金属400将由第一部分210包围的沟槽填充,并且沉积在第一部分210上。
在一个实施例中,在沉积金属400后,可通过蚀刻溶液将氧化层200的第一部分210除去。
这里,氧化层200的第一部分210能够通过剥离操作被除去。留在第一部分210上的部分金属400随着该氧化物一起除去,而位于第一部分之间的这部分金属400保留下来。
因此,如图9所示,第一金属线“a”和第二金属线“b”交替形成。
这里,第一和第二金属线“a”和“b”可具有不同的宽度,这取决于具有第一宽度d1的光刻胶图形310的分开距离(separationdistance)。
例如,假设相邻光刻胶图形310之间的分开距离为d3,氧化层200的厚度可给定为x,形成在半导体衬底100上并且在半导体凸起部110内部的氧化层200的厚度是x1,并且形成在半导体凸起部110外部的氧化层200的厚度是x2,其中x=x1+x2。
此外,假设第一金属线“a”的宽度是d2,该宽度是如图8所示的第二宽度,并且第二金属线“b”的宽度是d4,于是金属线的宽度可由d2=d1-2(x1)以及d4=d3-2(x2)来给出。这里,由于x1和x2是由实验所决定的因子,因此可通过控制宽度d1和d3将第一金属线“a”和第二金属线“b”的宽度设成彼此相等或者不同。
如上所述,根据一个实施例,通过使半导体器件的线形成得比用于限定半导体凸起部的光刻胶图形之间的宽度更窄,能够使得半导体器件小型化。
说明书中任何谈到“一个实施例”、“一实施例”、“示例性实施例”等指的是在本发明的至少一个实施例中包含有一个特定的特征,结构,或者与该实施例描述相关的特性。说明书中各个地方出现的这种措辞不一定指的是同一实施例。此外,当对特定的特征,结构或者特性与任一实施例相关地进行描述时,其落在本领域技术人员能够与这些实施例中的其他一个相关地影响这些特征,结构,或者特性的范围内。
尽管这里参照许多示例性实施例描述了本发明的实施例,但是应该理解,本领域技术人员能够对此进行其他的大量的落在公开内容的原理和范围内的修改和具体实施。特别是,对组件和/或落在公开内容、附图和所附权利要求书内的对象组合布置的各种布置,各种变化和修改都是可能的。在组件和/或布置的变化和修改之外,对本领域技术人员来说,选择使用也是显而易见的。

Claims (11)

1.一种用于制造半导体器件的方法,该方法包括:
在半导体衬底上形成具有第一宽度的光刻胶图形;
使用该光刻胶图形作为掩模蚀刻该半导体衬底,以形成半导体凸起部;
在包括该半导体凸起部的半导体衬底的整个表面上形成氧化层;
除去该半导体凸起部,以形成被该氧化层包围的沟槽;
在该沟槽上实施覆盖蚀刻,以仅仅留下一部分形成于该沟槽周围的氧化层;
在包括该部分氧化层的该半导体衬底的整个表面上沉积金属;并且
除去该部分氧化层,以形成金属图形。
2.如权利要求1所述的方法,还包括在利用该光刻胶图形作为掩模蚀刻该半导体衬底后,除去该光刻胶图形。
3.如权利要求1所述的方法,其中除去该半导体凸起部以形成该沟槽包括:
抛光该氧化层,以将该半导体凸起部暴露出来;以及
蚀刻该暴露的半导体凸起部,以除去该半导体凸起部。
4.如权利要求3所述的方法,其中蚀刻该暴露的半导体凸起部包括利用氟化乙烯丙烯选择性地湿法蚀刻该半导体凸起部。
5.如权利要求1所述的方法,其中形成该氧化层包括湿法氧化该半导体衬底的表面以形成该氧化层。
6.如权利要求5所述的方法,其中该湿法氧化是在900-1000℃温度下实施的。
7.如权利要求1所述的方法,其中该形成该氧化层使得该半导体凸起部具有比第一宽度窄的第二宽度。
8.如权利要求7所述的方法,其中该氧化层的厚度的40-50%是从该半导体凸起部形成的。
9.如权利要求1所述的方法,其中该实施覆盖蚀刻包括实施反应性离子蚀刻工艺,其中该氧化层是通过该反应性离子蚀刻工艺仅仅在高度方向上被除去的。
10.如权利要求1所述的方法,其中沉积金属包括使用电子束蒸发工艺来沉积铜。
11.如权利要求1所述的方法,其中该氧化层的厚度x由等式x=x1+x2给出,并且在形成该氧化层之后该半导体凸起部d2的厚度由等式d2=d1-2(x1)给出,
其中d1是第一宽度,x1是从该半导体凸起部中形成的部分氧化层的厚度,x2是从该半导体凸起部的外部形成的部分氧化层的厚度,并且
其中该金属图形包括具有宽度为d1的第一金属线和宽度为d3-2(x2)的第二金属线,
其中d3是该光刻胶图形之间的距离。
CNB2007101366443A 2006-07-18 2007-07-18 制造半导体器件的方法 Expired - Fee Related CN100527383C (zh)

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CN112462468A (zh) * 2020-10-27 2021-03-09 中国科学院微电子研究所 利用图形反转制作光子晶体的方法及光子晶体

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