KR940010395A - 박막트랜지스터의 제조방법 및 액정표시장치의 제조방법 - Google Patents

박막트랜지스터의 제조방법 및 액정표시장치의 제조방법 Download PDF

Info

Publication number
KR940010395A
KR940010395A KR1019930020765A KR930020765A KR940010395A KR 940010395 A KR940010395 A KR 940010395A KR 1019930020765 A KR1019930020765 A KR 1019930020765A KR 930020765 A KR930020765 A KR 930020765A KR 940010395 A KR940010395 A KR 940010395A
Authority
KR
South Korea
Prior art keywords
reaction chamber
semiconductor film
line
thin
silicon layer
Prior art date
Application number
KR1019930020765A
Other languages
English (en)
Other versions
KR0130955B1 (ko
Inventor
유끼히꼬 나까따
Original Assignee
쓰지 하루오
샤프 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 쓰지 하루오, 샤프 가부시끼가이샤 filed Critical 쓰지 하루오
Publication of KR940010395A publication Critical patent/KR940010395A/ko
Application granted granted Critical
Publication of KR0130955B1 publication Critical patent/KR0130955B1/ko

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
    • C23C16/5096—Flat-bed apparatus
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/54—Apparatus specially adapted for continuous coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

박막 트랜지스터가 표면을 가지는 절연막과, 상기 절연막상의 표면에 형성된 반도체막과, 상기 반도체막과 접하는 소스 전극 및 드레인 전극과, 반도체막으로부터 전기적으로 절연된 게이트 전극을 포함한다.
박막 트랜지스터에서, 상기 절연막의 표면으로부터 500 옹스트롬 이하 거리에서의 부분이 적어도 5×10-9s/㎝ 혹은 그 이상의 도전율의 미결정구조를 포함하는 실리콘을 포함한다.
또한 그러한 박막 트랜지스터를 제조하는 방법이 설명되어있다.
박막 트랜지스터를 제조하는 방법이, (1) 플라즈마 화학적 기상 성장 장치의 반응실에 도입된 실리콘을 포함하는 원료 가스를 분해하여 절연막상에 실리콘층을 형성하는 공정과, (2) 상기 반응실에 수소가스를 도입하여 상기 실리콘층에 수소 플라즈마 처리를 행하도록 실리콘층을 미결정화하는 공정과를 반복함으로써 미결정구조를 가지는 실리콘층을 포함하는 반도체막을 형성하는 공정은 포함한다.

Description

박막트랜지스터의 제조방법 및 액정표시장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 사용전 수소플라즈마처리를 가능하게 하는 RF-PCVD 장치의 일예를 나타내는 도,
제2도는 수소플라즈마 처리시간에 대한 실리콘막의 암도전율의 변화를 설명한 그래프,
제3도는 본 반명에 따른 일예의 액정표시장치의 주요부분은 나타낸 횡단면도,
제4도는 본 발명에 사용된 인-라인 CVD 장치를 나타낸 도.

Claims (11)

  1. 표면을 가지는 절연막과, 상기 절연막의 표면상에 형성된 i형의 반도체막과, 상기 반도체막과 접하는 소스전극 및 드레인 전극과, 상기 반도체막으로부터 전기적으로 절연된 게이트전극과른 포함하는 박막 트랜지스터에 있어서, 상기 절연막의 상기 도면으로부터 500옹스트롬 이하 거리에서의 상기 반도체막의 부분이, 적어도 5×10-3s/㎝ 혹은 그 이상의 도전율의 미결정구조를 가지는 실리콘을 포함하는 박막 트랜지스터.
  2. 표면을 가지는 절연막과, 상기 절연막의 표면상에 형성된 p형 혹은 n형의 반도체막과, 상기 반도체막으로부터 전기적으르 절연된 게이트전극과를 포함하는 박막 트랜지스터에 있어서, 상기 절연막의 상기 표면으로부터 500 옹스트롬 이하 거리에서의 상기 반도체막의 부분이, 적어도 1×10-9s/㎝ 혹은 그 이상의 도전율의 미결정구조를 가지는 실리콘을 포함하는 박막 트랜지스터.
  3. 표면을 가지는 절연막과, 상기 절연막의 표면상에 형성된 반도체막층, 상기 반도체막과 접하는 소스 전극 및 드레인 전극과, 상기 반도제막으로부터 전기적으로 절연된 게이트전극과를 포함하는 박막 트랜지스터에 있어서, 상기 절연막의 상기 표면으로부터 500 옹스트롬 이하 거리에서의 상기 반도체막의 부분이, 적어도 10원자% 혹은 그 이하인 미결정구조를 가지는 실리콘을 포함하는 박막 트랜지스터.
  4. 표면을 가지는 절연막층, 상기 절연막의 표면상에 형성된 반도체막과, 상기 반도체막과 접하는 소스 전극 및 드레인 전극측, 상기 반도체막으로부터 전기적으로 절연된 게이트전극과를 포함하는 박막 트랜지스터에 있어서, 상기 절연막의 상기 표면으로부터 500 옹스트롬 이하 거리에서의 상기 반도체막의 부분이, 적어도 10원자% 혹은 그 이상의 결정체적분율의 미결정구조를 가지는 실리콘을 포함하는 박막 트랜지스터.
  5. 박막 트랜지스터를 제조하는 방법이, (1) 플라즈마 화학적 기상 성장 장치의 반응실에 도입된 실리콘을 포함하는 원료가스를 분해하여 실리콘층을 형성하는 공정과, (2) 상기 반응실에 상기 수소 가스를 도입함으로써 상기 실리콘층에 수소 플라즈마 처리를 행하여 상기 실리콘층을 미결정화하는 공정과를, 반복적으로 수행함으로써 미결정구조를 가지는 실리콘층을 포함하는 반도체막은 형성하는 공정을 포함하는 박막 트랜지스터 제조방법.
  6. 제5항에 있어서, 상기 절연막상에 상기 반도체막은 형성하는 공정 이전에 상기 반도체막이 형성되는 상기 절연막의 상측 표면에 수소 플라즈마 처리를 하는 공정을 더욱더 포함하는 박막 트랜지스터의 제조방법.
  7. 제5항에 있어서, 상기 실리콘층을 형성하는 공정에 있어서, 상기 실리콘층이 1∼1000 옹스트롬의 범위내의 두께를 가지고 형성되는 박막트랜지스터 제조방법.
  8. 수소 희석은 200 혹은 그 이상인 상태에서, 100 옹스트롬 혹은 그 이상의 두께의 미결정구조를 가지는 실리콘층을 형성하는 제1공정과, 수소 희석을 2∼100인 상태에서 미결정구조를 가지는 또 다른 실리콘층을 상기 실리콘층상에 형성하는 제2공정과를 포함하는 박막 트랜지스터 제조방법.
  9. 박막 트랜지스터를 포함하는 액정 표시장치를 제조하는 방법에 있어서, 상기 박막 트랜지스터 각각에 대하여 반도체막을 형성하는 공정이, (1) 플라즈마 화학적 기상 성장 장지의 반응실에 도입된 실리콘은 포함하는 원료 가스를 플라즈마에 의하여 분해하여 기판상에 어모퍼스 실리콘층을 형성하는 공정과, (2) 상기 반응실에 수소가스를 도입하여 상기 어모퍼스 실리콘층에 수소 플라즈마 처리를 행하는 공정과를, 반복적으로 수행함으로써 미결정구조를 가지는 실리콘층으로 이루어지는 반도체막을 형성하는 공정을 포함하는 박막 트랜지스터를 포함하는 액정표시장치의 제조방법.
  10. 플라즈마 화학적 기상 성장 장치는, 얇은 반도체층은 형성하고 상기 얇은 반도체층에 수소 플라즈마 처리를 행하기위한 반응실과, 상기 반응실에 연결되어 상기 반응실에 수소 가스를 도입하기 위한 제1라인과, 상기 반응실에 관련되어 상기 얇은 반도체층을 형성하기 위하여 사용되는 원료가스를 상기 반응실에 도입하기 위한 제2라인과, 상기 제2라인에 연결되어 제2라인으로부터 상기 원료 가스를 배출하기위한 제3라인과, 상기 원료가스를 도입하기 위한 상기 제2라인과 상기 원료가스를 배출하기위한 상기 제3라인과의 사이를 스위칭하기위한 스위칭 수단과를 포함하는 플라즈마 화학적 기상 성장 장치.
  11. 얇은 반도체층은 형성하고 상기 얇은 반도체층에 수소 플라즈마처리를 행하기위한 반응실과, 상기 반응실에 연결되어 상기 반응실에 수소 가스를 도입하기위한 제1라인과, 상기 반응실에 연결되어 상기 얇은 반도체층을 형성하기 위하여 사용되는 원료가스를 상기 반응실에 도입하기 위한 제2라인과, 상기 제2라인에 연결되어 제2라인으로부터 상기 원료 가스를 배출하기위한 제3라인과, 상기 반응실과, 상기 제2라인과 제3라인의 연결부 사이의 제2라인상에 설치된 제1밸브와, 상기 제3라인상에 설치된 제2밸브와, 상기 제1과 제2밸브의 개폐를 제어하기 위한 제어수단과를 포함하는 플라즈마 화학적 기상 성장 장치에서, 상기 얇은 반도체층이 형성될때, 상기 제어수단이 상기 제1밸브를 열고 제2밸브를 담는 것을 제어하는 것에 의하여 상기 원료 가스가 상기 반응실로 도입되고, 또한 상기 수소 플라즈마 처리가 상기 얇은 반도체층에 행해질 때에는, 상기 제어수단이 상기 제2밸브를 열고 제1밸브를 닫는 것은 제어하는 것에 의하여 상기 원료 가스의 반응실에의 도입만을 차단하는 플라즈마화학적기상성장장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930020765A 1992-10-07 1993-10-07 박막 트랜지스터의 제조방법 및 액정표시장치의 제조방법 KR0130955B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26898192 1992-10-07
JP92-268981 1992-10-07

Publications (2)

Publication Number Publication Date
KR940010395A true KR940010395A (ko) 1994-05-26
KR0130955B1 KR0130955B1 (ko) 1998-04-14

Family

ID=17465999

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930020765A KR0130955B1 (ko) 1992-10-07 1993-10-07 박막 트랜지스터의 제조방법 및 액정표시장치의 제조방법

Country Status (3)

Country Link
US (1) US5686349A (ko)
EP (1) EP0592227A3 (ko)
KR (1) KR0130955B1 (ko)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078059A (en) * 1992-07-10 2000-06-20 Sharp Kabushiki Kaisha Fabrication of a thin film transistor and production of a liquid display apparatus
KR100327086B1 (ko) * 1994-06-15 2002-03-06 구사마 사부로 박막 반도체 장치의 제조방법, 박막 반도체 장치,액정표시장치 및 전자기기
US5796116A (en) * 1994-07-27 1998-08-18 Sharp Kabushiki Kaisha Thin-film semiconductor device including a semiconductor film with high field-effect mobility
US5677236A (en) * 1995-02-24 1997-10-14 Mitsui Toatsu Chemicals, Inc. Process for forming a thin microcrystalline silicon semiconductor film
FR2743193B1 (fr) * 1996-01-02 1998-04-30 Univ Neuchatel Procede et dispositif de depot d'au moins une couche de silicium hydrogene microcristallin ou nanocristallin intrinseque, et cellule photovoltaique et transistor a couches minces obtenus par la mise en oeuvre de ce procede
US5966627A (en) * 1996-08-30 1999-10-12 Lucent Technologies Inc. In-situ doped silicon layers
US6169013B1 (en) 1997-03-07 2001-01-02 Sharp Laboratories Of America, Inc. Method of optimizing crystal grain size in polycrystalline silicon films
US6329270B1 (en) 1997-03-07 2001-12-11 Sharp Laboratories Of America, Inc. Laser annealed microcrystalline film and method for same
WO2000063956A1 (fr) * 1999-04-20 2000-10-26 Sony Corporation Procede et dispositif pour realiser un depot de couches minces, et procede pour la production d'un dispositif a semiconducteur a couches minces
JP2004146691A (ja) * 2002-10-25 2004-05-20 Chi Mei Electronics Corp 微結晶薄膜の成膜方法、薄膜トランジスタの製造方法、薄膜トランジスタおよび薄膜トランジスタを用いた画像表示装置
US6841431B2 (en) * 2003-01-29 2005-01-11 Chunghwa Picture Tubes, Ltd. Method for reducing the contact resistance
EP1445802A1 (en) * 2003-02-06 2004-08-11 Centre National De La Recherche Scientifique (Cnrs) Transistor for active matrix display, a display unit comprising the said transistor and a method for producing said transistor
TWI399580B (zh) * 2003-07-14 2013-06-21 Semiconductor Energy Lab 半導體裝置及顯示裝置
US8142606B2 (en) * 2007-06-07 2012-03-27 Applied Materials, Inc. Apparatus for depositing a uniform silicon film and methods for manufacturing the same
JP2009049384A (ja) 2007-07-20 2009-03-05 Semiconductor Energy Lab Co Ltd 発光装置
JP2009054719A (ja) * 2007-08-24 2009-03-12 Tokyo Electron Ltd 半導体製造方法、半導体製造装置および表示装置
US20090090915A1 (en) 2007-10-05 2009-04-09 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, display device having thin film transistor, and method for manufacturing the same
WO2009063606A1 (ja) * 2007-11-15 2009-05-22 Sharp Kabushiki Kaisha 薄膜トランジスタ、薄膜トランジスタの作製方法、及び表示装置
CN101933148B (zh) * 2008-01-25 2012-12-05 夏普株式会社 半导体元件及其制造方法
US20100295047A1 (en) * 2008-01-25 2010-11-25 Masao Moriguchi Semiconductor element and method for manufacturing the same
US8575615B2 (en) * 2008-09-17 2013-11-05 Sharp Kabushiki Kaisha Semiconductor device
US20100086703A1 (en) * 2008-10-03 2010-04-08 Veeco Compound Semiconductor, Inc. Vapor Phase Epitaxy System
US8921857B2 (en) 2009-06-18 2014-12-30 Sharp Kabushiki Kaisha Semiconductor device
US8557687B2 (en) * 2009-07-23 2013-10-15 Semiconductor Energy Laboratory Co., Ltd. Method for forming microcrystalline semiconductor film and method for manufacturing thin film transistor
US8383434B2 (en) * 2010-02-22 2013-02-26 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and manufacturing method thereof
CN115132754B (zh) * 2022-06-30 2023-06-27 惠科股份有限公司 背光模组及其制备方法、显示面板

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723216A (en) * 1980-07-17 1982-02-06 Matsushita Electric Ind Co Ltd Manufacture of plasma reactor and semiconductor element
JPS5767020A (en) * 1980-10-15 1982-04-23 Agency Of Ind Science & Technol Thin silicon film and its manufacture
JPS5994810A (ja) * 1982-11-22 1984-05-31 Agency Of Ind Science & Technol アモルファスシリコン膜の製造法
JPS59139682A (ja) * 1983-01-31 1984-08-10 Ricoh Co Ltd 光導電性薄膜
JPS6179259A (ja) * 1984-09-26 1986-04-22 Seiko Instr & Electronics Ltd 薄膜トランジスタ装置
JPS639923A (ja) * 1986-07-01 1988-01-16 Matsushita Electric Ind Co Ltd 薄膜の製造方法
JPS6343157A (ja) * 1986-08-11 1988-02-24 Toshiba Corp 電子写真感光体
JPS6369220A (ja) * 1986-09-10 1988-03-29 Nec Corp ４族半導体薄膜の製造方法
JPS63157165A (ja) * 1986-12-19 1988-06-30 Kobe Steel Ltd 電子写真用感光体
JPH0775233B2 (ja) * 1987-09-14 1995-08-09 松下電器産業株式会社 大規模集積回路の製造方法
JPH01161826A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 気相エピタキシャル成長法
JPH01173640A (ja) * 1987-12-28 1989-07-10 Fujitsu Ltd 半導体装置の製造方法
JPH02159021A (ja) * 1988-12-13 1990-06-19 Agency Of Ind Science & Technol 微結晶の配向性制御方法
WO1990012126A1 (en) * 1989-03-31 1990-10-18 Canon Kabushiki Kaisha Method of forming polycrystalline film by chemical vapor deposition
US5194398A (en) * 1989-06-28 1993-03-16 Mitsui Toatsu Chemicals, Inc. Semiconductor film and process for its production
JPH03126222A (ja) * 1989-10-12 1991-05-29 Canon Inc 堆積膜形成方法
JPH04137525A (ja) * 1990-12-03 1992-05-12 Agency Of Ind Science & Technol シリコン薄膜剥離防止方法
JPH04266019A (ja) * 1991-02-20 1992-09-22 Canon Inc 成膜方法
JP2880322B2 (ja) * 1991-05-24 1999-04-05 キヤノン株式会社 堆積膜の形成方法
US5242530A (en) * 1991-08-05 1993-09-07 International Business Machines Corporation Pulsed gas plasma-enhanced chemical vapor deposition of silicon

Also Published As

Publication number Publication date
EP0592227A3 (en) 1995-01-11
KR0130955B1 (ko) 1998-04-14
EP0592227A2 (en) 1994-04-13
US5686349A (en) 1997-11-11

Similar Documents

Publication Publication Date Title
KR940010395A (ko) 박막트랜지스터의 제조방법 및 액정표시장치의 제조방법
US5180690A (en) Method of forming a layer of doped crystalline semiconductor alloy material
US7125758B2 (en) Controlling the properties and uniformity of a silicon nitride film by controlling the film forming precursors
KR100309627B1 (ko) 반도체장치제조방법
US5834071A (en) Method for forming a thin film transistor
US20020192885A1 (en) Fabrication process for thin film transistors in a display or electronic device
KR960005955A (ko) 박막 반도체 소자, 박막 트랜지스터 및 그의 제조방법
EP0556912B1 (en) Rapid plasma hydrogenation process for polysilicon MOSFET's
US7825414B2 (en) Method of forming a thin film transistor
Bernstein et al. Hydrogenation of polycrystalline silicon thin film transistors by plasma ion implantation
US6444507B1 (en) Fabrication process for thin film transistors in a display or electronic device
US20010012650A1 (en) Method of manufacturing thin film transistor
US5561074A (en) Method for fabricating reverse-staggered thin-film transistor
KR19980038871A (ko) 유사다이아몬드를 이용한 박막 트랜지스터 및 그의 제조방법
US20040198046A1 (en) Method for decreasing contact resistance of source/drain electrodes
JPH11121762A (ja) 液晶表示素子の薄膜トランジスタ及びその製造方法
US5970325A (en) Thin-film switching device having chlorine-containing active region and methods of fabrication therefor
KR100190146B1 (ko) 질소 함유 실리콘층 및 고융점 금속층으로 형성된 게이트 구조를 갖고 있는 전계 효과 트랜지스터의 제조 프로세스
JPS62200768A (ja) 薄膜トランジスタの製造方法
JPH05275702A (ja) 薄膜トランジスタ
JPH07153958A (ja) 薄膜トランジスタおよびその製造方法
KR960026968A (ko) 이중게이트를 구비한 박막트랜지스터 및 그 제조방법
KR20010003759A (ko) 박막 트랜지스터의 제조방법
Mishima et al. Effect of hydrogen ion shower doping in polycrystalline silicon thin‐film transistors
JPH0758337A (ja) 多結晶ＳｉＴＦＴの製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021107

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee