KR940008077A - 반도체 집적회로장치 - Google Patents

반도체 집적회로장치 Download PDF

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Publication number
KR940008077A
KR940008077A KR1019930019027A KR930019027A KR940008077A KR 940008077 A KR940008077 A KR 940008077A KR 1019930019027 A KR1019930019027 A KR 1019930019027A KR 930019027 A KR930019027 A KR 930019027A KR 940008077 A KR940008077 A KR 940008077A
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South Korea
Prior art keywords
power supply
terminal
digital circuit
substrate
circuit
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KR1019930019027A
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English (en)
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마사유키 고이즈미
하루유키 미야타
Original Assignee
사토 후미오
가부시키가이샤 도시바
오카모토 세이시
도시바 마이크로일렉트로닉스 가부시키가이샤
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Publication of KR940008077A publication Critical patent/KR940008077A/ko
Priority to KR2019980003356U priority Critical patent/KR0132100Y1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

본 발명은 디지탈회로부에서 발생한 노이즈를 확실하게 차단할 수 있고, 디지탈회로와 아날로그회로의 상호간섭을 충분히 방지할 수 있는 반도체 집적회로장치를 제공하고자 하는 것이다.
이를 위해 본 발명은, P형 실리콘기판(10)내에 N형 웰영역(12)과 N형 웰영역(14)을 설치하고, N형 웰영역(12)에 아날로그회로를 배치하며, N형 웰영역(14)에 디지탈회로를 배치하고, 기판(10)의 바이어스전위를 디지탈회로의 전원이외의 전원(GND2)으로부터 얻는 것을 주요한 특징으로 하고 있다. 이러한 구성에 의하면, 기판(10)의 전위를 디지탈회로의 전원이외의 전원으로부터 얻음으로써, 디지탈회로에서 발생한 노이즈가 전원배선을 매개해서 기판내로 침입하지 않게 된다. 이 때문에, 디지탈회로부에서 발생한 노이즈를 확실하게 차단할 수 있게 되어 디지탈회로와 아날로그회로의 상호간섭이 충분히 방진된다.

Description

반도체 집적회로장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체 집적회로장치의 단면도.
제2도는 본 발명을 적용할 수 있는 아날로그회로와 디지탈회로가 1개의 칩내에 집적되어 있는 반도체 집적회로의 블럭도.
제3도는 제2도에 도시된 아날로그/디지탈 커버터의 구성도.
제4도는 제2도에 도시된 아날로그/디지탈 컨버터의 다른 구성도.
제5도는 제2도에 도시된 디지탈/아날로그 컨버터의 구성도.
제6도는 본 발명의 제2실시예에 따른 반도체 집적회로장치의 단면도.

Claims (3)

  1. 제1도전형 반도체기체와, 상기 기체내에 형성된 아날로그회로, 상기 기체내에 형성된 디지탈회로, 상기 아날로그회로를 구성하기 위해 상기 기체의 표면영역내에 형성된 제1소자, 상기 디지탈회로를 구성하기 위해 상기 기체의 표면영역내에 형성된 제2소자, 상기 아날로그회로에 동작전원을 인가하는 제1전원수단, 상기 디지탈회로에 동작전원을 인가하는 제2전원수단, 상기 기체내에 형성되어 상기 제1소자 및 제2소자의 적어도 한쪽을 상기기체로부터 격리하는 제2도전형 반도체영역 및, 상기 제2전원수단이외의 전원으로부터 얻은 바이어스전위를 상기 기체에 인가하는 바이어스수단을 구비한 것을 특징으로 하는 반도체 집적회로장치.
  2. 제1항에 있어서, 상기 제1전원수단은, 제1고전위전원단자와, 이 제1고전위전원단자와 상기 아날로그회로를 상호 접속하는 제1배선, 제1저전위전원단자 및, 이 제1저전위전원단자와 상기 아날로그회로를 상호 접속하는 제2배선을 포함하고 있고, 상기 제2전원수단은, 제2고전위전원단자와, 이 제2고전위전원단자와 상기 디지탈회로를 상호 접속하는 제3배선, 제2저전위전원단자 및, 이 제2저전위전원단자와 상기 디지탈회로를 상호 접속하는 제4배선을 포함하고 있으며, 상기 바이어스수단을 적어도 상기 제2고전위전원단자 및 상기 제2저전위전원단자와는 다른 제3전원단자와 상기 기체를 상호 접속하는 제5배선을 포함하고 있고, 전류통로의 일단을 상기 제1고전위전원단자에 접속하고 그 타단을 상기 제3전원단자에 접속한 제1보호소자와, 전류통로의 일단을 상기 제2고전위전원단자에 접속하고 그 타단을 상기 제3전원단자에 접속한 제2보호소자를 포함하는 보호회로를 더 구비한 것을 특징으로 하는 반도체 집적회로 장치.
  3. 제1항 또는 제2항에 있어서, 상기 기체내에 형성되어 상기 아날로그회로의 주위를 둘러싸는 상기 기체보다 고농도의 제1도전형 제1반도체영역과, 상기 기체내에 형성되어 상기 디지탈회로의 주위를 둘러싸는 상기 기체보다 고농도의 제1도전형 제2반도체영역을 더 구비하고서, 상기 바이어스수단을 상기 제1, 제2반도체영역 각각에 접속하는 것을 특징으로 하는 반도체 집적회로장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930019027A 1992-09-25 1993-09-20 반도체 집적회로장치 KR940008077A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019980003356U KR0132100Y1 (en) 1992-09-25 1998-03-09 Semiconductor integrated circuit device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP25629692 1992-09-25
JP92-256296 1992-09-25
JP22436093A JP3251735B2 (ja) 1992-09-25 1993-09-09 半導体集積回路装置
JP93-224360 1993-09-09

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KR940008077A true KR940008077A (ko) 1994-04-28

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US4595909A (en) * 1981-11-25 1986-06-17 The United States Of America As Represented By The Secretary Of The Navy N-bit propagatary analog-to-digital converter system
JP3017809B2 (ja) * 1991-01-09 2000-03-13 株式会社東芝 アナログ・デジタル混載半導体集積回路装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020001938A (ko) * 2000-06-21 2002-01-09 김윤 극세 스펀본드 부직포의 제조방법

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