KR940004856A - 전계효과 트랜지스터 제조방법 - Google Patents
전계효과 트랜지스터 제조방법 Download PDFInfo
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- KR940004856A KR940004856A KR1019930013859A KR930013859A KR940004856A KR 940004856 A KR940004856 A KR 940004856A KR 1019930013859 A KR1019930013859 A KR 1019930013859A KR 930013859 A KR930013859 A KR 930013859A KR 940004856 A KR940004856 A KR 940004856A
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- film
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- 238000000034 method Methods 0.000 title claims description 11
- 230000005669 field effect Effects 0.000 title claims description 4
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract 6
- 238000005530 etching Methods 0.000 claims abstract 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract 5
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 3
- 239000000758 substrate Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 2
- 230000001678 irradiating effect Effects 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000002310 reflectometry Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/95—Multilayer mask including nonradiation sensitive layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/952—Utilizing antireflective layer
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
노출된 광이 실리콘 산화막(11)에 도달할때, 실리콘 산화막(11)에 다중반사된 빛이 포토레지스트층(15)을 확장시키거나 수축시킨다.
텅스텐 실리사이드막(13)은 노출된 광이 실리콘 산화막(11)에 도달하지 못하게 한다.
이 실리콘산화막(11)이 게이트 전극을 형성하기 위해 에칭에 의해 다결정 실리콘막(7)과 텅스텐 실리사이드막(9)을 선택적으로 제거하기 위한 마스크로서 사용되고, 텅스텐 실리사이드막(13)이 이 에칭에 의해 동시에 제거된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 전계효과 트랜지스터 제조방법에 있어서 노광공정을 표시하는 실리콘 기판 단면도이다;
제2도의 불투명막의 두께와 절대 반사값 사이의 관계를 표시하는 그래프이다;
Claims (10)
- 반도체 기판(1)의 주표면 위에 게이트 절연막으로서 사용되는 제1절연막(5)을 형성하는 공정과 ; 상기 제1절연막(5) 위에 게이트 전극을 정의하기 위한 도전막(7, 9)을 형성하는 공정과; 상기 도전막(7, 9) 위에 실리콘 산화막 또는 실리콘 질화막 중에서 적어도 하나를 포함하는 투명한 제2절연막(11)을 형성하는 공정과; 상기 제2절연막(11) 위에 다결정 실리콘막, 비결정 실리콘막, 텅스텐 실리사이드막 및 티타늄 질화막의 그룹으로부터 선택된 적어도 하나의 막을 포함하는 불투명막(13)을 형성하는 공정과 ; 상기 불투명막(l3)위에 포토레지스트층(15)을 형성하는 공정과 ; 상기 게이트 전극을 형성하기 위한 패턴닝을 하는 중에 상기 포토레지스트층(15)을 노광하기 위해 상기 포토레지스트층(15)에 광을 조사하는 공정과 ; 마스크로서 사용한 상기 포토레지스트층(15)을 통하여 상기 불투명막(13)을 선택적으로 제거하는 공정과 ; 상기 포토레지스트층(15)를 제거하는 공정과 ; 마스크로서 사용한 상기 불투명막(13)을 통하여 상기 제2절연막(11)을 선택적으로 제거하는 공정과 ; 상기 게이트 전극(21)을 형성하기 위해 마스크로서 사용한 상기 제2절연막(11)을 통하여 에칭에 의해 상기 도전막(7, 9)를 선택적으로 제거하고, 상기 에칭에 의해 상기 마스크로서 사용된 상기 불투명막(13)을 동시에 제거하는 공정으로 구성된 전계효과 트랜지스터 제조방법.
- 제1항에 있어서, 상기 불투명막(13)을 에칭할 수 있는 것과 균등하게 상기 도전막(7, 9)을 에치할 수 있는 전계효과 트랜지스터 제조방법.
- 제1항에 있어서, 상기 불투명막(13)과 상기 도전막(7, 9)이 같은 물질로 만들어질 수 있는 전계효과 트랜지스터 제조방법.
- 제1항에 있어서, 상기 불투명막(l3)이 적어도 350Å의 두께를 갖는 전계효과 트랜지스터 제조방법.
- 제1항에 있어서, 광에 대한 상기 불투명막(13)의 반사율이 적어도 30%이고 60% 이상이 아닌 전계효과 트랜지스터 제조방법.
- 반도체 기판(1)의 주표면위에 게이트 절연막으로서 사용되는 제1절연막(5)을 형성하는 공정과 ; 상기 제1절연막(5) 위에 게이트 전극을 정의하기 위한 도전막(7, 9)을 형성하는 공정과 ; 상기 도전막(7, 9) 위에 실리콘 산화막 또는 실리콘 질화막 중에서 적어도 하나를 포함하는 투명한 제2절연막(11)을 형성하는 공정과 ; 상기 제2절연막(11) 위에 다결정 실리콘막, 비결정 실리콘막, 텅스텐 실리사이드막과 티타늄 질화막의 그룹으로부터 선택된 적어도 하나의 막을 포함하는 불투명막(13)을 형성하는 공정과 ; 상기 불투명막(13) 위에 포토레지스트층(15)를 형성하는 공정과 ; 상기 게이트 전극을 형성하기 위한 패턴닝을 하는 중에 상기 포토레지스트층(15)을 노광하기 위해 상기 포토레지스트층(15)을 광을 조사하는 공정과 ; 마스크로서 사용한 상기 포토레지스트층(15)을 통하여 상기 불투명막(13) 및 상기 제2절연막(11)을 선택적으로 제거하는 공정과; 상기 포토레지스트층(15)를 제거하는 공정과 ; 상기 게이트 전극(21)을 형성하기 위해 마스크로서 사용한 상기 제2절연막(11)을 통하여 에칭에 의해 상기 도전막(7, 9)을 선택적으로 제거하고, 상기 불투명막(13)을 동시에 제거하는 공정으로 구성된 전계효과 트랜지스터 제조방법.
- 제6항에 있어서, 상기 불투명막(13)을 에치할 수 있는 것과 균등하게 상기 도전막(7, 9)을 에치할 수 있는 전계효과 트랜지스터 제조방법.
- 제6항에 있어서, 상기 불투명막(13)과 상기 도전막(7, 9)이 같은 물질로 만들어질 수 있는 전계효과 트랜지스터 제조방법.
- 제6항에 있어서, 상기 불투명막(13)이 적어도 350Å의 두께를 가진 전계효과 트랜지스터 제조방법.
- 제6항에 있어서, 광에 대한 상기 불투명막(13)의 반사율이 적어도 30%이고 60% 이상이 아닌 전계효과 트랜지스터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP92-207798 | 1992-08-04 | ||
JP4207798A JP2901423B2 (ja) | 1992-08-04 | 1992-08-04 | 電界効果トランジスタの製造方法 |
Publications (2)
Publication Number | Publication Date |
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KR940004856A true KR940004856A (ko) | 1994-03-16 |
KR970010653B1 KR970010653B1 (ko) | 1997-06-30 |
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Application Number | Title | Priority Date | Filing Date |
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KR1019930013859A KR970010653B1 (ko) | 1992-08-04 | 1993-07-21 | 전계효과 트렌지스터 제조방법 |
Country Status (4)
Country | Link |
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US (1) | US5302538A (ko) |
JP (1) | JP2901423B2 (ko) |
KR (1) | KR970010653B1 (ko) |
DE (1) | DE4318688C2 (ko) |
Families Citing this family (23)
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US5403759A (en) * | 1992-10-02 | 1995-04-04 | Texas Instruments Incorporated | Method of making thin film transistor and a silicide local interconnect |
US5891784A (en) * | 1993-11-05 | 1999-04-06 | Lucent Technologies, Inc. | Transistor fabrication method |
US5438006A (en) * | 1994-01-03 | 1995-08-01 | At&T Corp. | Method of fabricating gate stack having a reduced height |
JPH07245306A (ja) * | 1994-01-17 | 1995-09-19 | Sony Corp | 半導体装置における膜平坦化方法 |
JPH07263684A (ja) * | 1994-03-25 | 1995-10-13 | Mitsubishi Electric Corp | 電界効果トランジスタの製造方法 |
US5641708A (en) * | 1994-06-07 | 1997-06-24 | Sgs-Thomson Microelectronics, Inc. | Method for fabricating conductive structures in integrated circuits |
US5910021A (en) * | 1994-07-04 | 1999-06-08 | Yamaha Corporation | Manufacture of semiconductor device with fine pattens |
US5854132A (en) * | 1994-11-29 | 1998-12-29 | Advanced Micro Devices, Inc. | Method for exposing photoresist |
US5545588A (en) * | 1995-05-05 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of using disposable hard mask for gate critical dimension control |
US5604157A (en) * | 1995-05-25 | 1997-02-18 | Industrial Technology Research Institute | Reduced notching of polycide gates using silicon anti reflection layer |
US6150250A (en) * | 1995-07-05 | 2000-11-21 | Yamaha Corporation | Conductive layer forming method using etching mask with direction <200> |
KR100203896B1 (ko) * | 1995-12-15 | 1999-06-15 | 김영환 | 게이트 전극 형성방법 |
US6008121A (en) * | 1996-03-19 | 1999-12-28 | Siemens Aktiengesellschaft | Etching high aspect contact holes in solid state devices |
JP3047832B2 (ja) * | 1996-10-03 | 2000-06-05 | 日本電気株式会社 | 半導体装置の製造方法 |
US5846878A (en) * | 1997-02-28 | 1998-12-08 | Nec Corporation | Method of manufacturing a wiring layer in a semiconductor device |
KR20010021740A (ko) | 1997-07-11 | 2001-03-15 | 에를링 블로메, 타게 뢰브그렌 | 무선 주파수에서 사용되는 집적 회로 소자를 제조하는 방법 |
US6297170B1 (en) * | 1998-06-23 | 2001-10-02 | Vlsi Technology, Inc. | Sacrificial multilayer anti-reflective coating for mos gate formation |
JP2000077520A (ja) | 1998-08-28 | 2000-03-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US6191016B1 (en) * | 1999-01-05 | 2001-02-20 | Intel Corporation | Method of patterning a layer for a gate electrode of a MOS transistor |
US6410210B1 (en) * | 1999-05-20 | 2002-06-25 | Philips Semiconductors | Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides |
US6274488B1 (en) * | 2000-04-12 | 2001-08-14 | Ultratech Stepper, Inc. | Method of forming a silicide region in a Si substrate and a device having same |
US6420264B1 (en) * | 2000-04-12 | 2002-07-16 | Ultratech Stepper, Inc. | Method of forming a silicide region in a Si substrate and a device having same |
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US5045150A (en) * | 1986-09-11 | 1991-09-03 | National Semiconductor Corp. | Plasma etching using a bilayer mask |
JPS63292649A (ja) * | 1987-05-25 | 1988-11-29 | Nec Corp | 半導体装置の製造方法 |
US4838994A (en) * | 1987-06-26 | 1989-06-13 | Siemens Aktiengesellschaft | Method for structuring a copper and/or permalloy layer by means of dry etching |
JPH0634401B2 (ja) * | 1987-12-29 | 1994-05-02 | 株式会社精工舎 | 遮光性薄膜のエッチング方法 |
JPH01241162A (ja) * | 1988-03-23 | 1989-09-26 | Hitachi Ltd | 半導体装置のアルミニウム配線 |
JPH0258212A (ja) * | 1988-08-23 | 1990-02-27 | Nec Corp | 半導体装置の製造方法 |
JPH0279463A (ja) * | 1988-09-14 | 1990-03-20 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH02250321A (ja) * | 1989-03-24 | 1990-10-08 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPH03133129A (ja) * | 1989-10-19 | 1991-06-06 | Seiko Epson Corp | 半導体装置の製造方法 |
US5106786A (en) * | 1989-10-23 | 1992-04-21 | At&T Bell Laboratories | Thin coatings for use in semiconductor integrated circuits and processes as antireflection coatings consisting of tungsten silicide |
US5118384A (en) * | 1990-04-03 | 1992-06-02 | International Business Machines Corporation | Reactive ion etching buffer mask |
JPH0496220A (ja) * | 1990-08-03 | 1992-03-27 | Sony Corp | 配線形成方法 |
JP3080400B2 (ja) * | 1990-11-30 | 2000-08-28 | 三菱電機株式会社 | 半導体装置 |
JPH04209565A (ja) * | 1990-12-07 | 1992-07-30 | Fujitsu Ltd | 光ビーム溶融再結晶半導体装置およびその製造方法 |
-
1992
- 1992-08-04 JP JP4207798A patent/JP2901423B2/ja not_active Expired - Lifetime
-
1993
- 1993-05-21 US US08/065,327 patent/US5302538A/en not_active Expired - Lifetime
- 1993-06-04 DE DE4318688A patent/DE4318688C2/de not_active Expired - Lifetime
- 1993-07-21 KR KR1019930013859A patent/KR970010653B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH0661253A (ja) | 1994-03-04 |
DE4318688C2 (de) | 1996-02-01 |
US5302538A (en) | 1994-04-12 |
JP2901423B2 (ja) | 1999-06-07 |
KR970010653B1 (ko) | 1997-06-30 |
DE4318688A1 (de) | 1994-02-10 |
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