KR930018696A - 반도체장치의 커패시터 제조방법 - Google Patents

반도체장치의 커패시터 제조방법 Download PDF

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KR930018696A
KR930018696A KR1019920021231A KR920021231A KR930018696A KR 930018696 A KR930018696 A KR 930018696A KR 1019920021231 A KR1019920021231 A KR 1019920021231A KR 920021231 A KR920021231 A KR 920021231A KR 930018696 A KR930018696 A KR 930018696A
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oxide film
polycrystalline layer
forming
semiconductor device
capacitor
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KR960002097B1 (ko
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한기만
황창규
강덕동
최영제
윤주영
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김광호
삼성전자 주식회사
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Priority to JP4319086A priority patent/JP2596686B2/ja
Priority to EP92120331A priority patent/EP0557590A1/en
Priority to US08/025,421 priority patent/US5405801A/en
Publication of KR930018696A publication Critical patent/KR930018696A/ko
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Abstract

본 발명은 반도체장치의 커패시터 제조방법이 개시되어 있다. 그 내부에 불순물이 포함되도록 미세구조의 그레인들로 이루어지는 다결정층을 형성하고, 불순물이 포함되어 있는 상기 다결정층에 식각공정을 행하여 그 그레인 경계부분을 깍아냄으로써 다결정층의 표면을 조면화 한다. 산화막을 이용하거나, 1차조면화된 다결정층 표면 부분을 노출시킨 후에 이방성 식각을 하여, 미세 트레치 및 미세 기둥을 형성하거나, 에피텍시얼 성장시켜 에피텍시얼 그레인을 형성하여, 다결정층의 표면적을 더욱 증가시킨다. 단순한 공정에 의해, 규칙성 및 재연성이 있으며 셀커패시턴스 증가 및 조절이 용이하면서도 신뢰성이 있는 반도체장치의 커패시터를 제조할 수 있다.

Description

반도체장치의 커패시터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 일정한 증착 두께에서 증착 온도에 따른 다결정실리콘이 표면 형태(조면화 정도) 변화를 나타내는 일련의 SEM 사진으로 기술된 종래 기술을 나타낸다.
제2도는 일정한 온도(570℃)에서 증착 두께에 따른 다결정실리콘층의 표면 형태(조면화 정도) 변화를 나타내를 일련의 SEM 사진으로 기술된 종래기술을 나타낸다.
제9도 내지 제11도는 본 발명에 의한 반도체장치의 커패시티 제조방법의 제1실시예를 설명하기 위한 단면도들이다.

Claims (19)

  1. 제1전극, 유전체막 및 제2전극으로 이루어지는 반도체장치의 커패시터를 제조방법하는데 있어서, 상기 제1전극을 형성하기 위한 공정은, 반도체기판 상에, 그 내부에 불순물이 포함되도록 미세구조의 그레인들로 이루어지는 다결정층을 형성하는 공정, 불순물이 포함되어 있는 상기 다결정층에 식각공정을 행하여 그 그레인경계부분을 깍아냄으로써 다결정층의 표면을 조면화하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  2. 제1항에 있어서, 다결정층을 형성하는 상기 공정 이 후에, 상기 다결정층을 패터닝하는 공정을 추가하는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제1항에 있어서, 다결정층의 표면을 조면화하는 공정이전에, 결과를 전면에 산화막을 형성하는 공정, 및 상기 산화막을 제거하는 공정을 추가하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  4. 제1항에 있어서, 다결정층의 표면을 조면화하는공정 이 후에, 결과물 전면에 산화막을 형성하는 공정, 및 상기 산화막을 제거하는 공정을 추가하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  5. 제4항에 있어서, 다결정층의 표면을 조면화하는 공정 이 후에 상기 산화막을 형성하고, 상기 산화막이 형성되어 있는 결과물 전면에 상기 산화막을 식각대상으로 한 이방성식각 공정을 행하여 다결정층을 구성하는 그레인 사이에만 상기 산화막을 남김으로써 산화막으로 된 마스크를 형성하는 공정, 및 상기 산화막으로 된 식각마스크를 식각에 대한 마스크로 이용하여 조면화된 상기 다결정층을 소정깊이로 이방성식각함으로써 다결정층에 미세트렌치를 형성하는 공정을 추가하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  6. 제5항에 있어서, 상기 소정깊이는 상기 다결정층의 두께와 같거나 작은 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  7. 제4항에 있어서, 다결정층의 표면을 조면화하는 공정 이 후에 상기 산화막을 형성하고, 상기 산화막이 형성되어 있는 결과물 전면에 상기 산화막을 식각대상으로 한 이방성식각 공정을 행하여 다결정층을 구성하는 그레인 사이에만 상기 산화막을 남김으로써 산화막으로 된 에피텍시얼 마스크를 형성하는 공정, 및 상기 산화막으로 된 마스크로 이용하여 조면화된 상기 다결정층의 노출된 부분에 에피텍시얼 실리콘그레인을 성장시키는 공정을 추가하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  8. 제1항에 있어서, 상기 불순물은 다결정층을 증착할때, 또는 이 후에 도우프되는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  9. 제8항에 있어서, 다결정층의 표면을 조면화하는 상기 공정 이 후에, 결과를 전면에 상기 불순물을 재도우프하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  10. 제1항에 있어서, 상기 다결정의 그레인경계부분을 깍아냄으로써 다결정층의 표면을 조면화하는 공정은, 상기 불순물을 특히 잘 식각해내는 식각용액을 사용하여 진행하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  11. 제10항에 있어서, 상기 불순물로 인이온을 사용하고, 상기 식각용액으로 인산을 사용하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  12. 제3항에 있어서, 상기 산화막은 화학기상증착법이나 열산화법에 의해 형성되는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  13. 제1항에 있어서, 상기 다결정층으로 다결정실리콘막, 비정질 실리콘막 또는 반구모양의 그레인을 갖는 다결정실리콘층을 사용하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  14. 제1항에 있어서, 다결정층을 조면화하는 상기 커패시티 제조방법은 스택형, 트렌치형 및 스택-트렌치형구조의 적용되는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  15. 제1항에 있어서, 다결정층을 형성하는 상기 공정이전에, 상기 반도체기판 전면에 실리콘질화막 및 고온산화막을 적층하는 공정을 추가하고, 제1전극을 완성한 후에, 상기 고온산화막의 일부분을 제거해내는 공정을 추가하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  16. 제1전극, 유전체막 및 제2전극으로 이루어지는 반도체 장치의 커패시터를 제조 방법 하는데 있어서, 상기 제1전극을 형성하기 위한 공정은, 반도체기판 상에 표면을 조면화된 다결정층을 형성하는 공정, 상기 다결정충상에 산화막을 형성하고, 상기 산화막이 형성되어 있는 결과물 전면에 상기 산화막을 식각대상으로 한 이방성식각 공정을 행하여 다결정층을 구성하는 그레인 사이에만 상기 산화막을 남김으로써 산화물로 된 식각마스크를 형성하는 공정, 및 상기 산화막으로 된 식각마스크를 이용하여 조면화된 상기 다결정층을 소정깊이로 이방성식각함으로써 다결정층에 미세트렌치를 형성하는 공정을 포함함을 특징으로 하는 반도체장치의 커패시터 제조방법.
  17. 제16항에 있어서, 상기 소정깊이는 상기 다결정층의 두께와 같거나 작은 것을 특징으로 하는 반도체장치의 커패시터 제조방법.
  18. 제1전극, 유전체막 및 제2전극으로 이루어지는 반도체 장치의 커패시터를 제조 방법 하는데 있어서, 상기 제1전극을 형성하기 위한 공정은, 반도체기판 상에 표면을 조면화된 다결정층을 형성하는 공정, 상기 다결정층상에 산화막을 형성하고, 상기 산화막이 형성되어 있는 결과물 전면에 상기 산화막을 식각대상으로 한 이방성식각 공정을 행하여 다결정층을 구성하는 그레인 사이에만 상기 산화막을 남김으로써 산화물로 된 에피텍시얼 마스크를 형성하는 공정, 및 상기 에피텍시얼 마스크를 이용하여 조면화된 상기 다결정층의 노출된 부분에 에피텍시얼 그레인을 성장시키는 공정을 포함함을 특징으로 하는 반도체장치의 커패시터 제조방법.
  19. 제18항에 있어서, 상기 에피텍시얼 그레인 성장공정은 담체가스로서 수소가스를 사용하고, SiH2Cl2+HCl계를 사용하여 수행함을 특징으로 하는 반도체장치의 커패시터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920021231A 1992-02-28 1992-11-12 반도체장치의 커패시터 제조방법 KR960002097B1 (ko)

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JP4319086A JP2596686B2 (ja) 1992-02-28 1992-11-27 半導体装置のキャパシタ製造方法
EP92120331A EP0557590A1 (en) 1992-02-28 1992-11-27 Method for manufacturing a capacitor of a semiconductor device
US08/025,421 US5405801A (en) 1992-02-28 1993-03-01 Method for manufacturing a capacitor of a semiconductor device

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