EP0233248A1 - Dielectric isolation structure for integrated circuits - Google Patents

Dielectric isolation structure for integrated circuits

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Publication number
EP0233248A1
EP0233248A1 EP19860905057 EP86905057A EP0233248A1 EP 0233248 A1 EP0233248 A1 EP 0233248A1 EP 19860905057 EP19860905057 EP 19860905057 EP 86905057 A EP86905057 A EP 86905057A EP 0233248 A1 EP0233248 A1 EP 0233248A1
Authority
EP
European Patent Office
Prior art keywords
oxide
substrate
silicon
layer
process according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19860905057
Other languages
German (de)
French (fr)
Inventor
George Maheras
Michael Raymond Gulett
Samuel Yue Chiao
Gayle Wilburn Miller
Lorain Marie 616 Boston Post Road MURPHY
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of EP0233248A1 publication Critical patent/EP0233248A1/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Definitions

  • This invention relates to a process for forming a dielectric isolation structure on a silicon substrate.
  • the invention also relates to an integrated circuit structure.
  • the invention has a particular application in the manufacture of very large scale highly dense integrated circuits for providing deep isolation regions which are useful for example in preventing the latch-up phenomenon which is associated with CMOS circuits.
  • a process of the kind specified is known from an article by Endo et al. , "Novel Device Isolation Technology with Selective Epitaxial Growth", IEEE Transactions on Electron Devices, Vol. Ed-31, No. 9, September 1984, pages 1283-1288.
  • a silicon dioxide layer having a thickness in the range of about 0.5 to 2.0 microns is thermally growth on a silicon substrate and patterned to form desired isolation regions using a reactive sputter etching technique with CF4+H2 plasma.
  • a 0.1 micron thick silicon nitride or polysilicon film is deposited and removed everywhere except on the oxide sidewalls.
  • epitaxial silicon is selectively grown using a Si-_2Cl2+__2+HCl system at reduced pressure. The nitride or polysilicon film protects the Si ⁇ 2" substrate interface during the epitaxial growth.
  • the known process has the disadvantage that using a mask patterning and etching technique for forming the isolation regions from the deposited oxide layer results in difficulties in achieving precise mask alignment and in achieving the provision of very narrow insulator structure widths, such as are desirable when device dimensions are reduced and device densities increased.
  • a process for forming a dielectric isolation structure on a silicon substrate characterized by the steps of: forming on the substrate a polycrystalline silicon structure having at least one sidewall which defines the location for the isolation structure; forming oxide to a predetermined width on the sidewall by oxidation thereof; and selectively removing the remaining polycrystalline structure to leave intact the oxide formed thereon.
  • a process according to the invention has the advantage that since the oxidation of polysilicon is a readily controllable process, very thin, precisely aligned and precisely dimensioned insulator structures can be achieved.
  • an integrated circuit structure having isolation regions defined therein, including a semiconductor substrate, a plurality of oxide isolation regions formed on a surface of the substrate, and epitaxial silicon formed on the surface of the substrate between the oxide isolation regions, characterized in that said isolation regions are formed by lateral oxidation growth substantially parallel to the plane of the substrate surface.
  • FIGS. 1-6 are partial cross-section views of a substrate taken sequentially during the implementation of the present isolation and epitaxial growth process.
  • a silicon dioxide etch stop layer 11 is formed to a thickness such as 50 nanometers by deposition on or growth from the initial surface 10 of a silicon semiconductor wafer 9.
  • the oxide layer 11 can be quickly grown by thermal -oxidation of the substrate 9 using a temperature within the approximate range 850°C to 1000°C.
  • a doped polycrystalline silicon layer 12 is then formed on the oxide 11, preferably to a thickness which is equal to or greater than the desired height of the oxide isolation structure.
  • the polysilicon can be formed by any of a number of conventional techniques, such as chemical vapor deposition at 625°C using silane (SiE.4) at 300 mT pressure.
  • the polysilicon is doped during its formation by the addition to the reactant gases of the appropriate gases such as phosphine or diborane, or can be doped subsequent to its formation by ion implantation or by the deposition of phosphorous or boron glass and subsequent diffusion.
  • nitride layer 14 is conveniently formed on the polysilicon 12 by low pressure chemical vapor deposition at 800°C using dichlorosilane and ammonia.
  • a suitable thickness for the silicon nitride 14 is 40-50 nanometers.
  • a silicon dioxide layer 13 may be formed on the polysilicon 12 by thermal oxidation of the polysilicon and used to ease eventual removal of the silicon nitride 14.
  • the silicon dioxide layer can be 20-50 nanometers thick.
  • the oxide-nitride is patterned into a mask pattern 16 by using conventional photolithographic techniques to form a photoresist mask on the nitride, then etching the oxide and nitride using dry or wet etch techniques. Then, the polysilicon 12 is etched in the presence of the mask 16 to form polycrystalline structures 18-18 which define trenches 17-17 between the sidewalls 19-19 thereof. The sidewalls 19-19 define the desired location of the subsequently formed oxide isolation walls 21-21. As will be appreciated by those skilled in the art, the mask 16 is patterned so that the edges thereof define the desired substrate locations of the subsequently-formed oxide isolation structures, then the edge locations are replicated in the polysilicon by etching.
  • a highly anisotropic process such as reactive ion etching (RIE) is used.
  • RIE reactive ion etching
  • One suitable RIE technique uses sulfur hexafluoride, CHF3 and C 2 F 6' power density of about 1.0 watts/cm2 and pressure of about 600 mTorr.
  • the RIE etch can be used to etch the nitride 14 and oxide 13 as well as the polysilicon 12.
  • the isolation oxide wall structures 21-21 are formed on the polysilicon sidewalls, and thereby automatically positioned at. the desired substrate locations, by thermal oxidation at about 750-900°C. Because the polysilicon is highly doped relative to the substrate 9, much more oxide is grown on the polysilicon edge than on the substrate.
  • this technique of defining the oxide isolation wall structure by lateral oxidation of the polysilicon provides very wide latitude in selecting the positioning and spacing of the oxide structures 21-21 and in tailoring the precise width and height of the oxide structures to the particular circuit requirements.
  • oxide isolation 21-21 typically it is preferable to use a highly anisotropic etch process such as the above- described reactive ion etching.
  • RIE reactive ion etching
  • epitaxial single crystal silicon 22 is formed on the substrate surface 10 between the oxide isolation walls 21-21.
  • conventional epitaxial deposition techniques can be used such as the thermal decomposition of silane or the reduction of silicon tetrachloride.
  • Such well- known current technology is non-selective in that the monocrystalline silicon forms on top of the oxide isolation walls, as indicated at 23, as well as on the substrate between the walls.
  • the upper surface can be chemically or mechanically polished back as necessary to the desired oxide isolation height and planar surface 24.
  • One suitable technique involves the spin- on application of a relatively low viscosity organic layer (not shown) atop the surface 23 of FIG. 5. The spun-on material is caused to flow to a relatively smooth surface by the centrifugal force of the application or by a subsequent low temperature bake. Reactive ion etching, which etches the organic material, the silicon and the oxide at approximately the same rate, is then used to clear the organic layer from the upper surface and as shown in FIG. 6 thereby replicate the surface smoothness of the organic coating in the upper surface 24 defined by the epitaxial silicon 22 and the oxide 21.
  • the resultant epi/oxide structure 25 has been formed on (not in) the initial surface 10 of the silicon substrate 9 and features oxide walls 21-21 having both width and height which are tailored to the design of the particular circuit, not dictated by the process limitations.
  • epitaxial silicon regions 22 were defined between oxide isolation walls 21 which were approximately 0.3-0.4 micrometer wide and 0.7 micrometer tall (thick) formed on the silicon substrate 9.
  • a 50 nanometer thick silicon dioxide layer 11 was formed on the substrate 9 by thermal oxidation in oxygen at 1000°C.
  • a polysilicon film 12 was then deposited to a depth of 700 nanometers using pyrolysis of silane (Sil_4) at 625°C (conventional LPCVD) .
  • the film was next doped to a sheet resistance of 15 ohms per square by deposition of phosphorus glass from reaction of phosphorus oxychloride at 975°C, and subsequent diffusion of phosphorus in the same furnace.
  • the phosphorus glass layer was next removed by etching with 10:1 HF for 40 seconds.
  • the oxidation mask was formed using conventional LPCVD to form a 40 nanometer thick silicon nitride layer 14, followed by patterning and etching using conventional photolithography and plasma etching techniques to form the nitride into the mask 16.
  • the doped polysilicon 12 was then etched by conventional plasma techniques in the presence of the mask 16 to define 3 micrometer wide trenches 17.
  • the resulting polysilicon sidewalls 19 were then thermally oxidized at 775°C to form oxide isolation walls 21-21, which were approximately 0.3-0.4 nanometers wide and about 0.7 nanometers tall.
  • the nitride mask 16 prevented oxidation of the top surface of the poly structure 18, while the highly doped polysilicon provided very fast differential oxidation of the polysilicon 18 relative to the substrate 9.
  • the nitride 16, poly 18, and underlying oxide 11 in trench regions 17, were removed by phosphoric acid etching, at 155°C, then plasma polysilicon etching, and a timed etch in hydrofluoric acid solution.
  • the epitaxial silicon 22 was formed between the oxide isolation walls 21-21 by epitaxial deposition from dichlorosilane/hydrogen/hydrogen chloride at 1000°C and 50 Torr to a thickness of 0.7 micrometers. Since the selective process formed no epitaxial silicon atop the oxide walls, the resulting contour/topography was smooth and planar.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)

Abstract

Dans un procédé pour former une structure d'isolation diélectrique (21) sur un substrat de silicium (9), une fine couche de bioxyde de silicium (11) est formée sur le substrat de silicium (9), une couche polycristalline dopée (12) est formée sur la couche de bioxyde de silicium (11) et un masque d'oxyde-nitrure (16) est formé sur la couche policrystalline (12). En utilisant le masque (16), la couche policrystalline (12) est attaquée afin de former des structures policrystallines (18) définissant des tranchées (17) dont les parois latérales (19) sont verticales, la couche d'oxyde (11) servant à arrêter l'attaque. Ensuite, par oxydation thermique, des régions (21) aux parois latérales en oxyde sont formées sur les parois latérales (19), le masque (16) et les parties restantes des structures de polysilicium (18) et la couche d'oxyde (11) sont enlevées, du silicium épitaxial (22) se développant entre les régions d'isolation d'oxyde qui forment la structure d'isolation diélectrique désirée (21) pour le silicium épitaxial (22).In a method for forming a dielectric insulation structure (21) on a silicon substrate (9), a thin layer of silicon dioxide (11) is formed on the silicon substrate (9), a doped polycrystalline layer (12 ) is formed on the silicon dioxide layer (11) and an oxide-nitride mask (16) is formed on the policrystalline layer (12). By using the mask (16), the policrystalline layer (12) is attacked in order to form policrystalline structures (18) defining trenches (17) whose side walls (19) are vertical, the oxide layer (11) serving to stop the attack. Then, by thermal oxidation, regions (21) with the oxide side walls are formed on the side walls (19), the mask (16) and the remaining parts of the polysilicon structures (18) and the oxide layer (11 ) are removed, epitaxial silicon (22) developing between the oxide isolation regions which form the desired dielectric isolation structure (21) for the epitaxial silicon (22).

Description

DIELECTRIC ISOLATION STRUCTURE FOR INTEGRATED CIRCUITS
Technical Field
This invention relates to a process for forming a dielectric isolation structure on a silicon substrate.
The invention also relates to an integrated circuit structure.
The invention has a particular application in the manufacture of very large scale highly dense integrated circuits for providing deep isolation regions which are useful for example in preventing the latch-up phenomenon which is associated with CMOS circuits.
Background Art
The continuing development of very large scale highly dense lC*s and very high speed IC's is imposing increasingly stringent device size and fabrication requirements. As the technology moves toward increasingly small devices and their associated thin gate oxides and shallow junction depths, it becomes imperative that the IC fabrication techniques used not only be capable of physically forming the required ultra small highly dense devices and related structures such as interconnects, but also do not degrade the existing IC structures or the subsequently-formed structures. In short, there must be compatibility with both the history of the integrated circuit and the subsequent processing thereof.
A process of the kind specified is known from an article by Endo et al. , "Novel Device Isolation Technology with Selective Epitaxial Growth", IEEE Transactions on Electron Devices, Vol. Ed-31, No. 9, September 1984, pages 1283-1288. In the known process, a silicon dioxide layer having a thickness in the range of about 0.5 to 2.0 microns is thermally growth on a silicon substrate and patterned to form desired isolation regions using a reactive sputter etching technique with CF4+H2 plasma. Next, a 0.1 micron thick silicon nitride or polysilicon film is deposited and removed everywhere except on the oxide sidewalls. Then, epitaxial silicon is selectively grown using a Si-_2Cl2+__2+HCl system at reduced pressure. The nitride or polysilicon film protects the Siθ2" substrate interface during the epitaxial growth.
The known process has the disadvantage that using a mask patterning and etching technique for forming the isolation regions from the deposited oxide layer results in difficulties in achieving precise mask alignment and in achieving the provision of very narrow insulator structure widths, such as are desirable when device dimensions are reduced and device densities increased.
Disclosure of the Invention
It is an object of the present invention to provide a process for forming a dielectric isolation structure on a silicon substrate wherein the aforementioned disadvantage is alleviated.
Therefore, according to the present invention, there is provided a process for forming a dielectric isolation structure on a silicon substrate, characterized by the steps of: forming on the substrate a polycrystalline silicon structure having at least one sidewall which defines the location for the isolation structure; forming oxide to a predetermined width on the sidewall by oxidation thereof; and selectively removing the remaining polycrystalline structure to leave intact the oxide formed thereon.
It will be appreciated that a process according to the invention has the advantage that since the oxidation of polysilicon is a readily controllable process, very thin, precisely aligned and precisely dimensioned insulator structures can be achieved.
According to another aspect of the invention, there is provided an integrated circuit structure having isolation regions defined therein, including a semiconductor substrate, a plurality of oxide isolation regions formed on a surface of the substrate, and epitaxial silicon formed on the surface of the substrate between the oxide isolation regions, characterized in that said isolation regions are formed by lateral oxidation growth substantially parallel to the plane of the substrate surface.
Brief Description of the Drawings
Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:
FIGS. 1-6 are partial cross-section views of a substrate taken sequentially during the implementation of the present isolation and epitaxial growth process.
Best mode for Carrying out the Invention
Referring to FIG. 1, to implement the present process, initially, a silicon dioxide etch stop layer 11 is formed to a thickness such as 50 nanometers by deposition on or growth from the initial surface 10 of a silicon semiconductor wafer 9. The oxide layer 11 can be quickly grown by thermal -oxidation of the substrate 9 using a temperature within the approximate range 850°C to 1000°C. A doped polycrystalline silicon layer 12 is then formed on the oxide 11, preferably to a thickness which is equal to or greater than the desired height of the oxide isolation structure. The polysilicon can be formed by any of a number of conventional techniques, such as chemical vapor deposition at 625°C using silane (SiE.4) at 300 mT pressure. The polysilicon is doped during its formation by the addition to the reactant gases of the appropriate gases such as phosphine or diborane, or can be doped subsequent to its formation by ion implantation or by the deposition of phosphorous or boron glass and subsequent diffusion. Next, nitride layer 14 is conveniently formed on the polysilicon 12 by low pressure chemical vapor deposition at 800°C using dichlorosilane and ammonia. A suitable thickness for the silicon nitride 14 is 40-50 nanometers. A silicon dioxide layer 13 may be formed on the polysilicon 12 by thermal oxidation of the polysilicon and used to ease eventual removal of the silicon nitride 14. The silicon dioxide layer can be 20-50 nanometers thick.
Referring to FIG. 2, the oxide-nitride is patterned into a mask pattern 16 by using conventional photolithographic techniques to form a photoresist mask on the nitride, then etching the oxide and nitride using dry or wet etch techniques. Then, the polysilicon 12 is etched in the presence of the mask 16 to form polycrystalline structures 18-18 which define trenches 17-17 between the sidewalls 19-19 thereof. The sidewalls 19-19 define the desired location of the subsequently formed oxide isolation walls 21-21. As will be appreciated by those skilled in the art, the mask 16 is patterned so that the edges thereof define the desired substrate locations of the subsequently-formed oxide isolation structures, then the edge locations are replicated in the polysilicon by etching. A highly anisotropic process such as reactive ion etching (RIE) is used. One suitable RIE technique uses sulfur hexafluoride, CHF3 and C2F6' power density of about 1.0 watts/cm2 and pressure of about 600 mTorr. The RIE etch can be used to etch the nitride 14 and oxide 13 as well as the polysilicon 12. Referring to FIG. 3, next the isolation oxide wall structures 21-21 are formed on the polysilicon sidewalls, and thereby automatically positioned at. the desired substrate locations, by thermal oxidation at about 750-900°C. Because the polysilicon is highly doped relative to the substrate 9, much more oxide is grown on the polysilicon edge than on the substrate. As will be readily appreciated by those skilled in the art, this technique of defining the oxide isolation wall structure by lateral oxidation of the polysilicon provides very wide latitude in selecting the positioning and spacing of the oxide structures 21-21 and in tailoring the precise width and height of the oxide structures to the particular circuit requirements.
As shown in FIG. 4, it is necessary to remove the mask 16 and the polycrystalline silicon 18 without removal of the oxide walls 21. This can be done using a selective etchant such as phosphoric acid at 155°C to remove the nitride 14, followed by the application of a selective etchant such as buffered hydrofluoric acid to remove the optional, thin oxide layer 13, if it is used (the short etch times required for this purpose leave the thick oxide structures 21 essentially unaffected) , followed by the application of a selective etchant such as a dry plasma poly etch using sulfur hexafluoride and freon 115 to remove the polysilicon structures 18-18 and the use of a brief etch in buffered 7:1 HF.to remove oxide 11. However, because the application of nominally selective etchant may tend to remove small amounts of the oxide isolation 21-21, typically it is preferable to use a highly anisotropic etch process such as the above- described reactive ion etching. RIE is highly desirable in that it leaves intact the essentially vertical walls of the oxide isolation structures 21- 21. Next, epitaxial single crystal silicon 22 is formed on the substrate surface 10 between the oxide isolation walls 21-21. Referring to FIG. 5, conventional epitaxial deposition techniques can be used such as the thermal decomposition of silane or the reduction of silicon tetrachloride. Such well- known current technology is non-selective in that the monocrystalline silicon forms on top of the oxide isolation walls, as indicated at 23, as well as on the substrate between the walls. In contrast, and referring to FIG. 6, if a selective epitaxial deposition technique is used, deposition of the monocrystalline silicon proceeds from the substrate without significant formation occurring on the oxide isolation walls 21. Selective epitaxial formation, thus, has the capability of providing the desired smooth, essentially planar upper surface topography 24. One of the several available suitable epitaxial silicon processes is referenced in the above Endo papers. As mentioned, this process uses Si__2Cl2+__2 systems, typically with about one volume percent HC1, and exemplary temperature and pressure of 1000°C and 50 Torr, respectively. The process provides good planarity and crystallinity in addition to selectivity.
After the selective or non-selective epitaxial deposition, the upper surface can be chemically or mechanically polished back as necessary to the desired oxide isolation height and planar surface 24. One suitable technique involves the spin- on application of a relatively low viscosity organic layer (not shown) atop the surface 23 of FIG. 5. The spun-on material is caused to flow to a relatively smooth surface by the centrifugal force of the application or by a subsequent low temperature bake. Reactive ion etching, which etches the organic material, the silicon and the oxide at approximately the same rate, is then used to clear the organic layer from the upper surface and as shown in FIG. 6 thereby replicate the surface smoothness of the organic coating in the upper surface 24 defined by the epitaxial silicon 22 and the oxide 21. The resultant epi/oxide structure 25 has been formed on (not in) the initial surface 10 of the silicon substrate 9 and features oxide walls 21-21 having both width and height which are tailored to the design of the particular circuit, not dictated by the process limitations.
In a specific working example, epitaxial silicon regions 22 were defined between oxide isolation walls 21 which were approximately 0.3-0.4 micrometer wide and 0.7 micrometer tall (thick) formed on the silicon substrate 9. Initially, a 50 nanometer thick silicon dioxide layer 11 was formed on the substrate 9 by thermal oxidation in oxygen at 1000°C. A polysilicon film 12 was then deposited to a depth of 700 nanometers using pyrolysis of silane (Sil_4) at 625°C (conventional LPCVD) . The film was next doped to a sheet resistance of 15 ohms per square by deposition of phosphorus glass from reaction of phosphorus oxychloride at 975°C, and subsequent diffusion of phosphorus in the same furnace. The phosphorus glass layer was next removed by etching with 10:1 HF for 40 seconds. The oxidation mask was formed using conventional LPCVD to form a 40 nanometer thick silicon nitride layer 14, followed by patterning and etching using conventional photolithography and plasma etching techniques to form the nitride into the mask 16. The doped polysilicon 12 was then etched by conventional plasma techniques in the presence of the mask 16 to define 3 micrometer wide trenches 17. The resulting polysilicon sidewalls 19 were then thermally oxidized at 775°C to form oxide isolation walls 21-21, which were approximately 0.3-0.4 nanometers wide and about 0.7 nanometers tall. During the isolation oxidation, the nitride mask 16 prevented oxidation of the top surface of the poly structure 18, while the highly doped polysilicon provided very fast differential oxidation of the polysilicon 18 relative to the substrate 9. Subsequently, the nitride 16, poly 18, and underlying oxide 11 in trench regions 17, were removed by phosphoric acid etching, at 155°C, then plasma polysilicon etching, and a timed etch in hydrofluoric acid solution. Following the etch, the epitaxial silicon 22 was formed between the oxide isolation walls 21-21 by epitaxial deposition from dichlorosilane/hydrogen/hydrogen chloride at 1000°C and 50 Torr to a thickness of 0.7 micrometers. Since the selective process formed no epitaxial silicon atop the oxide walls, the resulting contour/topography was smooth and planar.
The above-described processes and parameters are merely exemplary of the implementation of the novel process. The crux of the process resides not so much in the specific parameters by which it is implemented, as in the use of silicon or other material to precisely define the location of the oxide isolation structure on the substrate, and the controlled oxide growth on the silicon sidewalls to precisely dimension and shape the isolation structure prior to the growth of epitaxial silicon and/or the formation of IC structures in the isolation regions.

Claims

1. A process for forming, a dielectric isolation structure on a silicon substrate (9), characterized by the steps of: forming on the substrate (9) a polycrystalline silicon structure (18) having at least one sidewall (19) which defines the location for the isolation structure; forming oxide
(21) to a predetermined width on the sidewall (19) by oxidation thereof; and selectively removing the remaining polycrystalline structure (18) to leave intact the oxide (21) formed thereon.
2. A process according to Claim 1, characterized by the step of forming epitaxial silicon
(22) on the substrate (9) in a region adjacent the oxide structure (21) .
3. A process according to Claim 2, characterized in that said epitaxial silicon (22) is selectively formed on said substrate (9) .
4. A process according to Claim 2 or Claim 3, characterized by the step of forming the epitaxial silicon (22) and the oxide isolation structure (21) to a smooth, essentially planar surface (24) .
5. A process according to any one of Claims 1 to 4, characterized in that said polycrystalline silicon .structure (18) has an oxidation rate which is greater than that of the substrate (9).
6. A process according to Claim 1, characterized by the step of forming a silicon dioxide layer (11) on said silicon substrate (9) prior to the formation of said polycrystalline silicon structure (18).
7. A process according to any one of Claims 1 to 6, characterized in that said step of selectively removing the remaining polycrystalline structure (18) is effected by reactive ion etching.
8. A process according to any one of Claims 3 to 7, characterized in that said epitaxial silicon (22) is selectively formed using a SiH Cl2+H2+HCl system.
9. A process according to Claim 1, characterized in that said polycrystalline silicon structure (18) is formed by depositing a polycrystalline silicon layer (12) on said substrate, forming a mask (16) on said polycrystalline silicon layer (12) , and etching the polycrystalline silicon layer (12) in the presence of said mask (16) .
10. A process according to Claim 9, characterized in that said step of forming oxide (21) is effected in the presence of said mask (16) .
11. A process according to Claim 9 or Claim 10, characterized in that said mask includes an oxide layer (13) formed on the polycrystalline silicon structure (18) and a nitride layer (14) formed on the oxide layer (13) .
12. An integrated circuit structure having isolation regions defined therein, including a semiconductor substrate (9), a plurality of oxide isolation regions (21) formed on a surface of the substrate (9) , and epitaxial silicon (22) formed on the surface of the substrate (9) between the oxide isolation regions (21) , characterized in that said isolation regions (21) are formed by lateral oxidation ii
growth substantially parallel to the plane of substrate surface.
EP19860905057 1985-08-15 1986-08-04 Dielectric isolation structure for integrated circuits Pending EP0233248A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76577385A 1985-08-15 1985-08-15
US765773 1985-08-15

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EP0233248A1 true EP0233248A1 (en) 1987-08-26

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450439A (en) * 1987-08-21 1989-02-27 Oki Electric Ind Co Ltd Manufacture of semiconductor device
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