JPS6310899B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to semiconductor devices, particularly bipolar large-scale integrated circuits, etc., in which grooves and the like for forming element isolation regions are formed by reactive sputter etching. Concerning the shaping of etched surfaces.

(b) Technical Background It is believed that further improvements in the cost performance of information processing devices will depend on the semiconductor devices used in these devices.
There is a strong push toward increasing the number of memory elements.

Bipolar large-scale integrated circuit (hereinafter referred to as LSI)
Also, rapid improvements have been made in terms of integration scale, circuit speed, power consumption, etc., and this has been achieved through comprehensive advances in process technology and circuit technology.

Element isolation technology in bipolar integrated circuits
Advances in LSI technology have played a large part in the progress in process technology, contributing to both increased integration and improved characteristics.

(c) Conventional technology and problems In the junction isolation method that has been used since the birth of integrated circuits as an element isolation technology, reverse biased
While a large parasitic capacitance occurs in the p-n junction,
Isoplanar methods have been proposed that significantly reduce parasitic capacitance and device isolation regions by providing the necessary isolation with an oxide film barrier, and a cross-sectional view is shown in Figure 1. IOP
(Isolation with Oxide and Polysilicon) or VIP (V-groove Isolation)
An element isolation method called polycrystal backfill has already been put into practical use in bipolar memory LSIs.

In FIG. 1, 1 is a p ^- -Si substrate, and the surface index of the surface is (100). 2 is n ⁺ -buried layer,
3 is a p ⁺ -channel cut layer, 4 is an n ^- epitaxial growth layer, and 5 is a SiO ₂ film. For the element classification region A and the collector isolation region B, a SiO ₂ film 6 is formed in a V-groove formed by anisotropic etching using a potassium hydroxide (KOH) solution, and polycrystalline Si 7 is filled in the SiO ₂ film 6 on the surface. It is formed by forming the film 8.

However, in device isolation using this V-groove IOP method, the width of the device isolation region B is limited by conditions in the depth direction such as the thickness of the epitaxial growth layer 4, which limits the improvement of LSI integration. There is.

In order to solve this problem, a method has recently been proposed in which the V-groove IOP method is expanded and device isolation trenches are formed in a letter-like shape by reactive sputter etching of Si. The already known reactive sputter etching method for forming U-grooves uses carbon tetrachloride (CCl ₄ ) or a mixed gas in which about 20% oxidation (O ₂ ) is added to CCl ₄ as an etchant. It is.

However, addition of CCl ₄ or O ₂
The reactive sputter etching method using CCl ₄ as an etchant has the following problems. That is, as shown in the cross-sectional view of FIG. 2, the p ^- -Si substrate 11
If the n ⁺ -buried layer 12, the n ^- -epitaxial growth layer 13, the SiO ₂ film 14, and the Si ₃ N ₄ film 15 are provided in the trench and the groove is formed by the etching method, the buried layer with a high impurity concentration is formed. Side etching occurs in the layer 12, and the shape of the groove is undercut as shown in the figure, which becomes an obstacle in the subsequent manufacturing process and deteriorates the characteristics and reliability of the LSI.

The inventor added the above CCl ₄ or O ₂
In order to solve the problems in the reactive sputter etching method using CCl ₄ as an etchant,
A reactive sputter etching method using a gas mixture of CCl ₄ and boron trichloride (BCl ₃ ) was proposed. The outline of the proposal will be explained below using examples.

FIG. 3 is a sectional view of this embodiment. In the figure, 21 is a p ^- -Si substrate, 22 is an n ⁺ -buried layer, and 2 is
3 is an n ^- -epitaxial growth layer, and 24 is a SiO ₂ film. A silicon nitride (Si ₃ N ₄ ) film and a phosphosilicate glass (PSG) film (both not shown in the figure) are provided on the SiO ₂ film 24, and using the PSG film as a mask, CCl ₄ and BCl ₃ A U-shaped groove is formed at a depth penetrating the n ⁺ -buried layer 22 by reactive sputter etching using a gas mixture with the etchant, and a SiO ₂ film 25, A p ⁺ region 26 serving as a channel cut is provided at the bottom of the u-groove, and then polycrystalline Si 27 is filled in the u-groove, and an SiO ₂ film 28 is formed on the surface of the polycrystalline Si 27.

As mentioned earlier, in the reactive sputter etching method, it is possible to remove undercuts in buried layers with high impurity concentrations by using an etchant in which BCl ₃ is added to CCl ₄ to enhance sputtering properties. can. However, when such an etching method with strong sputtering property is applied to a silicon substrate, the following problems occur.

That is, as shown in the cross-sectional view in FIG. 4a, for example, an n ⁺ -buried layer 32 and an n ^- epitaxial growth layer 33 are formed on a p ^- -Si substrate 31, and an SiO ₂ film 34,
A pattern is formed in advance on the Si ₃ N ₄ film 35 and the PSG film 36, and using the PSG film 36 as a mask, the above-mentioned CCl ₄
When forming the U-groove 37 by reactive sputter etching using an etchant with strong sputtering properties, such as a _mixed gas of A notch 38 occurs at the bottom edge.

If the SiO ₂ film 39 is formed on the inner wall of the U-groove with such a shape, as shown in the cross-sectional view of FIG. This results in crystal defects being induced in the substrate 31, which impairs the characteristics and reliability of semiconductor devices such as LSIs.

(d) Purpose of the Invention The present invention involves selectively etching grooves or the like on a silicon substrate by reactive sputter etching with a strong sputtering property for device isolation of bipolar LSIs and other purposes. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not cause the above-mentioned damage to the silicon substrate, particularly the substrate, when an oxide film is subsequently formed on the etched surface.

(e) Structure of the Invention The above objects of the present invention include a step of selectively etching a semiconductor substrate by reactive sputter etching to form a groove in the semiconductor substrate, and wet etching the exposed surface of the semiconductor in the groove. This is achieved by a manufacturing method including a step of forming an insulating film in the groove.

(f) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.

FIGS. 5a and 5b are sectional views showing the first embodiment of the present invention, and the outline will be explained going back to the beginning of the manufacturing process.

As shown in FIG. 4a, n-type impurities such as arsenic (As) and antimony (Sb) are diffused over the entire surface of a p ^- -Si substrate 31 to form an n ⁺ -buried layer 32, and then n ^- -epitaxy is applied. A layer 33 is formed, and then a layer 33 is deposited to a thickness of approximately
100 [nm] SiO ₂ film 34, about 200 [nm] thick
A Si ₃ N ₄ film 35 and a phosphosilicate glass (hereinafter referred to as PSG) film 36 with a thickness of about 1.0 [μm] are sequentially formed, and the PSG film 36 at a position to be used as an element isolation region, the Si ₃ N ₄ film 35 and
The SiO ₂ film 34 is selectively removed.

The substrate is then placed in a reactive sputter etching chamber, for example on parallel plate electrodes, and treated with CCl ₄ 100
The mixed gas is introduced to a pressure of about 0.1 [Torr] at a flow rate ratio of about 50 to 100 [cc/min] to BCl ₃ [cc/min], for example about 70 [cc/min], and the mixture is heated to 500 [W].
By applying high frequency power of about 1 to 1 [KW], for example, about 650 [W], the U-shaped groove 37 penetrates the epitaxial layer 33 and the n ⁺ -buried layer 32 and reaches the semiconductor substrate 31. Form to the desired depth.

At this time, as described above, a notch 38 as shown in the figure is generated at the bottom of the U-groove 37.

Therefore, according to the _present invention, after the reactive sputter etching shown in FIG. The etched surface shown in FIG. 4a is shaped into a smooth shape by etching at a rate of 150 to 200 nm per minute. This state is shown in Figure 5a.
Shown below.

FIG. 5b shows a state in which this shaped etched surface is oxidized to form a SiO ₂ film 39.

Further, FIGS. 6a and 6b are sectional views showing a second embodiment of the present invention.

In this embodiment, the surface index of the surface of the p ^- -Si substrate 31 is set to (100), and the U groove 37 shown in FIG. 4A is provided in the same manner as in the previous embodiment. After that
Wet etching with KOH for example at a temperature of 70
[°C] for about 10 seconds to 1 minute to shape the etched surface into the smooth shape shown in FIG. A SiO ₂ film 39 is formed by oxidizing the surface.

When using an isotropic etchant such as the mixed solution of HNO ₃ and HF in the first embodiment, the surface index of the substrate is not restricted and the influence of the difference in impurity concentration can be ignored. In order to have an etching effect, the groove width in reactive sputter etching must be narrower than the intended groove width by an amount equivalent to wet etching.

Furthermore, when using an anisotropic etchant such as the KOH solution in the second embodiment, the plane index of the substrate is limited to (100) and it is necessary to limit the etching time.

(g) Effects of the Invention As explained above, the present invention is intended to apply the expanded IOP method to device isolation of bipolar LSIs, etc. by using a mixed gas of CCl ₄ and BCl ₃ as an etchant. After forming a groove with vertical side surfaces on the silicon substrate surface by highly reactive sputter etching, isotropic or anisotropic wet etching is performed to remove the notch formed at the bottom of the groove. By shaping the etched surface and then forming an oxide film on the etched surface, it prevents stress from occurring on the substrate, improves the characteristics and reliability of semiconductor devices, and contributes to increased integration. It is something to do.

[Brief explanation of the drawing]

1 to 3 and FIGS. 4a and 4b are cross-sectional views showing a conventional example, and FIGS. 5a and b, and FIGS. 6 a and b are cross-sectional views showing an embodiment of the present invention. In the figure, 1 is a Si substrate, 2 is a buried layer, 3 is a channel cut layer, 4 is an epitaxial growth layer, and 5 is a buried layer.
is SiO ₂ film, 6 is SiO ₂ film, 7 is polycrystalline Si layer 8 is
SiO ₂ film, 11 is a Si substrate, 12 is a buried layer, 13 is an epitaxial growth layer, 21 is a Si substrate, 22 is a buried layer, 23 is an epitaxial growth layer, 24 is a
SiO ₂ film, 25 is SiO ₂ film, 26 is p ⁺ region, 27 is polycrystalline Si layer, 28 is SiO ₂ film, 31 is Si substrate, 32
33 is an epitaxial growth layer, 34 is a buried layer, and 34 is an epitaxial growth layer.
35 is a Si ₃ N ₄ film, 36 is a PSG film, ₃₇ is a groove, 38 is a notch, and 39 is a SiO ₂ film.

Claims (1)

[Claims] A semiconductor substrate having a plane index of (100) is selectively etched by reactive sputter etching,
A step of forming a groove in the semiconductor substrate, and an anisotropic etching solution that depends on the direction of the (111) plane of the substrate and exposes the (111) plane, relieves the cut at the corner of the groove bottom surface. , and the bottom surface is V
1. A method of manufacturing a semiconductor device, comprising the steps of: etching to such an extent that no shape is formed; and forming an insulating film in the groove.