JPS60226135A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize high integration density of LSI by forming a first and a second films on the one main surface of a semiconductor substrate, removing the second film at the level-different section, forming a sharp groove to the one main surface of substrate, and thereafter burying the groove with an insulator which becomes the inter-element isolation layer. CONSTITUTION:After a thin thermal oxide film is formed on the surface N<-> type silicon semiconductor substrate 11, a silicon nitride film 12 is deposited. The surface is then coated with a PSG film 13 and moreover a photo resist film 14. Next, it is then patterned. A plasma nitride film 16 is deposited on the entire surface of semiconductor substrate 11 and this film 16 is then etched. The PSG film 13 is removed by the lift-off processing. When the semiconductor substrate 11 is dry-etched, a sharp groove 18 is formed on the surface of semiconductor substrate. After, the ion of N type impurity 19 such as phosphorus, etc. is implanted and the semiconductor substrate 11 is heat-processed at a high temperature. An insulator insulator 23 consisting of SiO2 is left only at the groove 18 by etching back of the SiO2 film 23 with dry-etching method and the inter- element isolation layer 10 obtained by burying the groove 18 with insulator completed.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to semiconductor device manufacturing technology, and more specifically, to isolation between elements and suppression of latch-up phenomena such as CMO3 in the semiconductor device manufacturing process. It concerns body separation technology.

[Background technology] Conventionally, in general, isolation between elements in LSI is as follows.

LOG OS (Local OxidaLion
of 5ilicon) method was often used. L.O.
The CO3 method is a technique for selectively oxidizing silicon on a substrate using an oxidation-resistant silicon nitride film as a mask. but.

This has the problem that bird's beaks occur at the edges of the oxide film due to selective oxidation, and these bird's beaks become a major obstacle to higher integration (for example, the magazine "Nikkei Electronics J," March 29, 1982 issue, 90th
(See page 101). It is difficult to reduce this bird's beak to a predetermined value, for example, 0.5 μm or less. Therefore, the influence of bird's beak becomes more significant as the minimum width anatomical value (mask dimension) becomes smaller.

On the other hand, complementary metal-insulator semiconductor devices, such as CMO
For S devices, measures against latch-up have become an important issue. Latch-up is a phenomenon in which parasitic transistors form a thyristor and excessive current continues to flow between the power supply and ground (Magazine [Nikkei Electronics J, 198
(See June 21, 2016 issue, page 146).

Here, an outline of an example of the process of forming a P-well structure for a CMOS device using the LOCO3 method will be described in Section 1-1.
This will be explained with reference to the drawings (the detailed configuration is shown in, for example, Japanese Patent Laid-Open No. 53-62487). In this step, first, as shown in FIG. 1(, ), a thermal oxide film 2 is formed on an N-type substrate wafer 1, and a photoresist film 3 is applied thereon. After patterning this, the same figure (b)
As shown in the figure (C), boron 4, which is a P-type impurity, is selectively ion-implanted, and then the photoresist film 3 is removed and well diffusion is performed to form a P-type well region 5, as shown in Figure (C). Form. This P-type well region 5 is a region for forming an N-channel MO3 element. After this, although not shown in the figure, it was lightly thermally oxidized, and then the same figure (d)
), a silicon nitride film 6 is applied, and this is patterned using a photoresist film 7 as shown in FIG. After this, the photoresist film 7 is removed, and L'0CO8 oxidation is performed using the silicon nitride film 6 as a mask, as shown in FIG. 3(f).

Thereby, the P-type well region 5 formed in the N-channel MO3 element and the N-type region of the base Fi1 forming the P-channel MO8 element can be separated by the 5i02 insulating layer 9. Then, as shown in (g) and (h) of the figure, by removing the silicon nitride film 6 and the oxide film 2, a stage is entered in which N-channel and P-channel MO3 elements are formed. Each MO3 element is formed by a normal process.

However, the techniques described above have the following three major drawbacks. Specifically, one reason is that the width of the element isolation insulating layer 9 becomes larger than the mask dimension due to the occurrence of bird's beaks, the second reason is that the impurity constituting the well region 5 spreads laterally, and the third reason is that Because the insulating layer 9 does not have a sufficient depth partly due to the bird's beak, the latch-up phenomenon described above tends to occur, and as a result, the degree of integration cannot be increased very much.

[Objective of the Invention] An object of the present invention is to create a groove with no bird's beak, deep grooves, and to enable high integration of LSI.
The object of the present invention is to provide a new element isolation technology that has no difference in dimensional conversion from photoresist.

Another object of the present invention is to provide a new element isolation technique for suppressing the latch-up phenomenon of CMO3.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

First, as a premise, the element isolation layer of the semiconductor device here has a structure in which a trench is filled with an insulating material.

This structure has many advantages over the LOCO3 method, and each advantage is summarized in the comparative diagram of FIG. In the element isolation layer 9 formed by the conventional LOCO3 method shown in FIG. 2(a), the bird's beak Δa is large, so if the mask dimension is a, the effective width of the element isolation layer 9 is a+2×Δa. Furthermore, as long as the N-channel and P-channel MO8 elements are separated using the LOCO3 method, the depth tl of the isolation layer 9 will be shallower than the depth t2 of the P-type well region 5, effectively reducing the spacing between the pixel elements. It cannot be made longer. On the other hand, in the device isolation layer 10 having the trench-embedded structure shown in FIG. 2(b), by making the bird's beak zero, the effective width of the isolation layer can be made to match the mask dimension a. . Moreover, the separation layer 1-0
The depth of can be made as deep as t3 (t+<<t3). Since the value of t3 is sufficiently larger than 11, C
This is also advantageous in terms of measures against MO3 latch-up. The inter-element isolation layer 10 having such a trench-buried structure is formed here by taking advantage of the fact that a film formed by plasma CVD is etched abnormally faster at stepped portions than at other portions.

[Example 1] Figures 3(a) to (j) show the difference in level of a silicon nitride film (this is the second film, hereinafter referred to as the plasma nitride film) produced by the plasma CVD method. FIG. 6 shows a standard process according to an embodiment of the present invention using an abnormally fast etching phenomenon and lift-off of the first PSG (phosphosilicate glass) film.

First, as shown in FIG. 3(a), a thin thermal oxide film is formed as a buffer on the surface of an N-type silicon semiconductor substrate 11 (not shown in the drawing), and then a silicon nitride film 12 is formed thereon. Then, PSGSiC1 and a photoresist film 14 are applied. Next, this is patterned to form the P-type well region, and the upper PSGSiC1 silicon nitride film 22 is etched off. At this time, by slightly overetching, a cut 15 is made in the silicon nitride film 12 as shown in FIG. 3(b).

After this, as shown in FIG. 3(C), the semiconductor substrate]
Plasma nitrite 1 to film 16 are applied to the entire surface of -1. When the plasma nitride film 1-6 is etched in this state as shown in FIG. The nitride film 16 is etched off, and the silicon surface of the semiconductor substrate 11 is exposed at that portion. Then, when PSGSiC1 is removed by lift-off processing, the result is as shown in FIG. 3(e). In this state, the semiconductor substrate 11 is dry-etched using the plasma nitride film 16 and silicon nitride #12 as a mask. Then, as shown in Figure 3(f),
A steep groove 18 is formed on the surface of the semiconductor substrate. Next, when this is entirely dry-etched, only the thin silicon nitride film 12 is etched off. After this, as shown in FIG. 3(g), an N-type impurity such as phosphorus 1
9 is ion-implanted to provide a high concentration at a location 20 where an N-type well region is to be formed. Then, when this semiconductor substrate 11 is heat-treated at a high temperature in such a state, a P-type well region 21 and an N-type well region 22 are simultaneously formed as shown in FIG. 3(h). As shown in FIG. 3(i), after forming a Si◯2 film 23 by CVD at high temperature and low pressure, a Si◯2 film 23 is formed by dry etching. As a result, the insulator 23 made of SiC2 is left only in the groove 18, and as shown in FIG.
0 is completed.

Here, each of N-channel type and P-channel type MO3FE is placed in the semiconductor substrate 11 having both P-type and N-type well regions 21 and 22 as shown in FIG. 3(j).
The memory element Static RAM (SRAM) is fabricated by CMO3 standard processes such as forming T! : Formed. In this SRAM, the degree of integration can be approximately doubled in the case of a 2 μm process configured with the same design rules as the conventional one, and moreover, defects due to latch-up phenomenon are significantly reduced compared to the SRAM with the conventional structure.

[Example 2] Figures 4 (,) to (i) are based on an example of the present invention that utilizes the abnormally high-speed etching phenomenon at the stepped portion of the plasma nitride film and the slowing down of the etching rate due to ion implantation of polysilicon. Demonstrate a standard process.

First, an N-type silicon semiconductor substrate 1 shown in FIG.
1, a 5i02 film 24 is formed by thermal oxidation, a polysilicon film 25 and a silicon nitride film 12 are formed thereon, and a photoresist film 14 is applied thereon.

After patterning, the silicon nitride film 12 located in the portion where the P-type well region is to be formed is etched off to form a structure as shown in FIG. 4(b). In this state, boron 26 is ion-implanted into the polysilicon 25,
Slow down the speed when etching. Then, the same Poron was ion-implanted with even higher energy, and the fourth
As shown in Figure (C), a P type implantation layer 27 for forming a P type well region is formed. Next, Figure 4 (d
), a plasma nitride film 16 is deposited. When the plasma nitride film 16 is etched in this state, the etching progresses rapidly at the stepped portion 17 of the plasma nitride film]-6, as shown in FIG. 4(e).
The second layer polysilicon film 25 is exposed at that portion.

Next, as shown in FIG. 4(f), the polysilicon film 25 and the thermal oxide film 24 are selectively etched off using the plasma nitride film 16 as a mask. After that, when the polysilicon film 25 is etched after removing the silicon nitride film 16°1-2, the etching rate is extremely slow in the ion-implanted polysilicon part.
As shown in FIG. 4(g), only the polysilicon that has not been ion-implanted is removed. Next, in this state, an N-type impurity 19 such as phosphorus is ion-implanted to form an implantation layer 20. After completely removing the remaining polysilicon 25, heat treatment is performed at high temperature to form a P-type well region 21 and an N-type well region 22 as shown in FIG. 4(h). . In this state, in the same manner as in Example 1, 5i02
adhesion.

By dry etching, an element isolation layer 1-0 is completed in which the groove 18 is filled with an insulator (S i 02 ) 23 as shown in FIG. 4(i).

Here, when the SRAM was formed in the same manner as in Example 1, the same effects as before were obtained.

[Effects] (1) Unlike the conventional LOCO8 method, bird's beak is reduced, so the degree of LSI integration can be significantly increased. This is mainly based on the fact that the extraordinarily high speed etching at the stepped portion of the film by the plasma CVD method is fairly controllable.

(2) The effect of (1) above is particularly remarkable in CMOS devices. This is because in the case of CMO3, the degree of integration has increased and each of the N-channel type and P-channel type MO
This is because, as the distance between the three elements becomes shorter, defects due to latch-up phenomenon increase, but as described above, with the trench-buried structure inter-element isolation layer, the degree of integration can be increased without worrying about latch-up.

(3) Also, since it is a trench-embedded structure, it is possible to prevent impurities in the P-type well region from spreading in the lateral direction.

(4) Furthermore, since the trench can be formed in a self-aligned manner, the element isolation layer and both wells can also be formed in a self-aligned manner.

Although the invention made by the present inventor has been specifically explained above based on Examples, it is to be understood that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Not even.

[Field of Application] The present invention applies to SR, which is a CMOS device described in the embodiment.
In addition to AM, DRAM (
Figure 1 (a)-(h) shows L
FIG. 2 is a process cross-sectional view showing an example of a process using the OCO8 method. FIG. (b) is an enlarged sectional view showing the latter, FIGS. 3(a) to (j) are process sectional views showing the process of Example 1 of this invention, and FIGS. 4(a) to (i) are views of this invention. FIG. 3 is a process cross-sectional view showing the process of Example 2.

DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Thermal oxide film, 3... Photoresist film, 4... Boron (P-type impurity), 5...
P-type well region, 6... silicon nitride film,
7... Photoresist film, 8... Boron ion, 9...
... Inter-element isolation layer by LOCO8 method, 10... Inter-element isolation layer with trench-buried structure, 11... Semiconductor substrate, 12
...Silicon nitride film, 13...PSG film (
14... Photoresist film, 15... Notch, 16... Plasma nitride film (second film)
, 17... Step portion, 18... Groove, 19... N type impurity, 21... P type well region, 22... N type well region, 23... S i 02 ( insulator), 2
4...Thermal oxide film, 25...Polysilicon Fig. 1 r/L) Fig. 1<e) Fig. 3 rθ-) Fig. 3 Fig. 41a Fig. 4

Claims (1)

[Claims] 1-1 A method for manufacturing a semiconductor device in which an element isolation layer has a structure in which a groove is filled with an insulating material, characterized by comprising at least the following steps: A method for manufacturing a semiconductor device. (A) A step of forming a first film having a stepped portion on one main surface of a semiconductor substrate, and then forming a second film by plasma CVD on the substrate including the first film. (B) A step of removing the second film at the step portion by taking advantage of the fact that the second film formed by plasma CVD is etched faster at the step portion than at other portions. (C) One side of the groove is defined by one end of the second film from which the stepped portion has been removed, and the other side of the groove is defined in relation to the stepped portion of the first film, so that the substrate is A process of forming steep grooves on one main surface. (D) A step of filling the trench in step (C) with an insulator and using it as the inter-element isolation layer. 2. Manufacturing a semiconductor device according to claim 1, wherein the other side of the groove in the step (C) is defined by an edge of a lower layer film that is side-etched from a stepped portion of the first film. Method. 3. The second film on the lower layer film is removed together with a portion of the first film by lifting off the first film before forming the groove in the step (C). A method for manufacturing a semiconductor device according to claim 2. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first film is formed with the polysilicon film on the substrate sandwiched therebetween. 5. The polysilicon film has an impurity introduced into a portion located on one side of the groove, and the polysilicon is selectively removed by utilizing a difference in etching rate due to a difference in impurity concentration. A method for manufacturing a semiconductor device according to item 4. 6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the first film is made of phosphosilicate glass, and the second film is made of silicone 1-light. .