JPS62112346A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make pattern alignment of high precision unnecessary, and improve manufacturing yield, by forming a stopper region on only a part of the side wall of a groove and the bottom of the groove by applying self alignment, at the time of forming a channel stopper region to prevent the generation of parasitic channel in an element isolation region of the groove type. CONSTITUTION:SiO2 film 2, Si3N4 film 3 and SiO2 film 4 are laminated and stuck on a P-type silicon substrate 1. The film 4 of a region containing a groove 10 to form a channel stopper region is eliminated, and instead a Si3N4 film 7 is formed anew between two grooves 10. By applying this film to a mask, etching is performed to make two groves 10 which penetrate the films 3 and 2 and enter into the substrate 1. Using hydro-fluoric acid as the buffer solution, side etching regions 11 are made in the remaining film 4, and the width of the surface part of the grove 10 is widened. Then a P-type impurity ion is implanted into only the upper side wall and the bottom of the groove 10 to form channel stopper regions 13 and 14 respectively, and a polycrystalline Si film 17 is burried into the groove 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a channel stopper for preventing parasitic channels in trench type element isolation.

[Conventional technology]

Groove-type element isolation is an excellent element isolation method for high-density integrated circuits because the isolation width between elements can be made extremely fine. However, due to the formation of parasitic channels on the groove sides,
There is a drawback that isolation between elements is incomplete. In order to improve this, a method has conventionally been used in which channel stoppers are formed on the side surfaces and the bottom of the groove. For example, the complementary MO8 field effect transistor formed on a T-shaped silicon substrate is abbreviated as CCMO8FF:T. ) using the groove type element isolation method, for example, Japanese Patent Laid-Open No. 59-16185
As shown in Publication No. 9 (hereinafter referred to as "publicly known material"), a method is used in which high concentration layers of opposite conductivity types are ion-implanted into opposing groove side surfaces using respective resist masks. The outline of the manufacturing process disclosed in the known materials is shown in FIGS. 4A to 4C. First, Figure 4A
As shown in the figure, after forming a silicon nitride film 3 having an opening 30 wider than the width of the groove to be formed, only one side of the opening 30 is covered with a resist 51, and boron ions are implanted. Form layer 52. 1 is a silicon substrate, and 2 is a silicon oxide film. Next, as shown in FIG. 4B, the other side of the opening 50 is covered with a resist 33, and phosphorus ions are implanted to form a phosphorus ion-implanted layer 34. As shown in Figure 4C, ? J136 is obtained by etching the silicon substrate 1 using the silicon oxide film frame 35 provided on the side wall of the opening 30 and the silicon oxide film 3 as a mask. A carrier killer layer 59 doped with gold or the like is provided at the bottom of the groove to improve the wound latch-up effect.

37 is a V single layer, and 38 is an N single layer.

[Problem that the invention seeks to solve]

In conventional methods as disclosed in known documents, ions must be implanted using separate resist masks patterned on the side surfaces of opposing grooves, which has the disadvantage of increasing the number of steps. Furthermore, the edges of the resist pattern must be present in the region where the grooves are to be formed, and extremely high accuracy alignment of the butterflies 7 is required. For example, width 0
．． When using 5 μm grooves, pattern misalignment must be controlled to 0.25 μm or less, which has a significant impact on the manufacturing yield of integrated circuit devices.

[Means for solving problems]

In order to solve the conventional problems, the present invention provides a method for manufacturing a semiconductor device in which a channel stopper layer is simply manufactured on one side of an element isolation groove formed around a well using a self-line process, comprising: a step of sequentially laminating a first thin film and a second thin film on a main surface of a conductive type silicon substrate in a region other than a region where a well of a conductive type different from that of the silicon substrate is to be formed; and masking the second thin film. a step of implanting ions of a conductivity type different from that of the silicon substrate into the silicon substrate to form a well; a step of under-etching the first thin film using the second thin film as a mask; and forming the well. depositing a third thin film on the region and the second thin film, lifting off the third thin film deposited on the second thin film by removing the second thin film; and the step of lifting off the third thin film deposited on the second thin film; forming a groove in the main surface of the silicon substrate using the first thin film and the third thin film as masks, and etching the end face of the pattern of the first thin film in contact with the groove to retract the end face. a step of implanting ions of the same conductivity type as that of the silicon substrate into the main surface of the silicon substrate and the bottom of the groove in a region where the end face of the first thin film pattern is side-etched; It is characterized in that it includes a step of embedding a fourth thin film. .

[For production]

The main feature of the present invention is that a channel stopper layer is formed by self-line on one side and the bottom of a fine groove, and no resist patterning is required to form a channel stopper.

In addition, a channel stopper can be formed at the same time on one side of the fine groove and on the bottom of the well.

Grooves and channel stoppers can be formed in cell 7 alignment using just one patterned resist mask. Examples will be described below based on the drawings.

〔Example〕

In the first embodiment, a case will be described in which an n-type well is formed on a p-type silicon substrate. When forming a p-type well on an n-type silicon substrate, it can be performed in the same manner as in the first embodiment by simply changing the conductivity type of the channel stopper.

1A to 1J are diagrams for explaining the steps of the first embodiment of the present invention, which will be described in detail below.

As shown in Figure 1A, for example, a specific resistance of 3 to 5 Ω/p
A silicon oxide film 2 with a thickness of 201 m to 70 nm is formed on a shaped silicon substrate 1. Thickness 1100ft to 200mm
A well should be formed by laminating in this order a silicon nitride film 3 and a silicon oxide film 4 with a thickness of 1 μm to 1 μm as the first thin film, and a butter-blackened resist 5 as the second thin film. A well region 6 is defined.

Next, the silicon oxide film 4 is etched using the butter-blackened resist 5 as a mask. For example, C
Reactive ion etching (hereinafter referred to as RI) using F, and hydrogen
It is abbreviated as E. ) is used.

Next, using the resist 5 as a mask, for example, phosphorus ions are implanted into the silicon substrate as an n-type impurity for forming a well. (FIG. 1B) As shown in FIG. 1C, the silicon oxide film 4 is under-etched using, for example, a buffered hydrofluoric acid solution. The underetch t defines the width of the groove formed around the well region in the following process, so for example 04
It is set to 5 μm.

Next, as shown in the first diagram, the third thin il scratch and 1.2
For example, silicon nitride! ! ! I7 as electronic cyclotro? The layer is deposited to a thickness of 1 μm to 2 μm by the resonance ridge deposition method (hereinafter abbreviated as ECR deposition method). Since the ECR'@horizontal deposition method can be performed at room temperature, a silicon nitride film can be deposited without causing thermal transformation to the resist pattern.

The under-etched region 8 where the silicon oxide film 4 is side-etched becomes a shadow of the resist pattern formed by the resist 5, so the silicon nitride film 7 is not deposited solely in the under-etched region 8. Furthermore, in the ECR quasi-volume method, the silicon nitride film 9 attached to the side surface of the step portion has extremely sparse texture and is therefore easily removed by a buffered hydrofluoric acid solution.

After removing the silicon nitride film 9 on the side surface of the stepped portion with a buffered hydrofluoric acid solution, the silicon nitride film 7 on the resist 5 is lifted off by removing the resist 5 with a mixed solution of flowing acid and hydrogen peroxide, for example. A cross-sectional shape shown in FIG. 1E is obtained.

Next, after etching the silicon nitride film 5 and the silicon oxide film 2 in the under-etched region 8 by the above-mentioned RIE, the silicon substrate 1 is etched by RIE using, for example, chlorine to form a groove with a depth of, for example, about 5 to 5 μm. 10 (FIG. 1F). When ions implanted into the well region are to be diffused deeper than the implanted layer, a high temperature heat treatment is performed at, for example, 1000° C. to 1150° C. in a nitrogen atmosphere. When performing high-temperature heat treatment after groove formation, a thickness of 10 mm is applied to the inner surface of the groove to avoid phosphorus outdiffusion.
After forming a silicon oxide film with a thickness of 30 nm to 30 nm, high temperature heat treatment is performed.

Next, the silicon oxide film 4 is side-etched to define a side-etched region 11 in contact with the groove 10. The side etched region 11 is a region where ions are implanted to form a channel stopper layer on the side surface of the groove 10, as described below, and its width is 0.1 μm to 0.5 μm.

For the side etching, for example, a buffered hydrofluoric acid solution is used. Since the main surface of the silicon oxide film 4 is etched at the same time by this etching, the silicon oxide film 4 is thinned by the same amount as the side etching amount. Next, using the silicon oxide film 4 and the silicon nitride film 7 as masks, ions of, for example, boron are implanted as a p-type impurity. In order to form a channel stopper layer on the side surface of the trench 10, ion implantation is performed at an acceleration energy of, for example, 70 KeV and 17 CJKeV. In order to have perfect masking properties for ion implantation, the thickness of silicon oxide film 4 during ion implantation must be 0.7 μm or more.

After the above-mentioned two ion implantations with different acceleration energies, a heat treatment of 30 minutes at 1050° C. in nitrogen, for example, is performed to form a groove with a depth of 0 at the top of one side of the groove 10 and at the bottom of the groove 10.
．． Channel stopper layers 16 and 14 with a thickness of 5 μm to 0.8 μm are formed (σ in FIG. 1).

Next, the silicon oxide film 4 is removed using the buffer valve ai, and approximately 1
Silicon nitride films 7 and 3 are removed using phosphoric acid heated to 60°C.
is removed, and the silicon oxide film 2 is removed again using a buffered hydrofluoric acid solution. Next, the surface of the silicon substrate 1 including the inner wall of the groove 10 is oxidized to 10? A silicon oxide film 15 with a thickness of tWL to 5071 m is formed, a silicon nitride film 16 is deposited by the CVD method, and a fourth thin film, for example, a polycrystalline silicon film 17 is buried in the trench 10 by the CVD method (FIG. 1H). .

The polycrystalline silicon film 17 is removed from the region other than the trench 10 by dry etching with, for example, CF and oxygen, and the trench 1 is removed.
Leave it almost completely within 0. Next, the surface of the polycrystalline silicon sliding door 17 left in the groove 10 is heated to 900°C to 1100°C.
to obtain a silicon oxide film 18 (first diagram).

Next, after removing the silicon nitride film 16 and silicon oxide film 15 in the area other than the groove 10 with phosphoric acid and buffered hydrofluoric acid solution heated to about 160° C., a gate oxide II $19 is formed by a normal process, For example, the gate electrode 20 is formed using doped polycrystalline silicon. Next, after covering the n-type well region with resist (not shown)
For example, arsenic is ion-implanted as an n-type impurity to form a diffusion layer 21 which will become the source and drain of the FET.

Next, after removing the resist, areas other than the n-type well region are covered with a resist (not shown), and p-type impurities, such as boron, are ion-implanted to form the p-type (which will become the source and drain of the O8 FET). A diffusion layer 22 is formed. Next, as an interlayer layer 23, for example, doped silicon oxide Ill is deposited, a contact hole is opened, and a wiring 2 is formed.
4, for example, patterning aluminum (first
Figure J).

In this embodiment, the polycrystalline silicon film 17 is used as the fourth thin film to fill the trench 10, but a silicon oxide film deposited by CVD may also be used. It goes without saying that this embodiment can also be applied to a substrate in which epitaxial silicon is formed on a highly doped substrate. In doing so, care should be taken to dig the trench deep enough to reach the high exposure substrate.

FIGS. 2A to 2C are cross-sectional views of a semiconductor device at main steps in a second embodiment of the present invention.

The case of forming a silicon oxide film will be described.

After obtaining the structure shown in FIG. 1H according to the method described in the first embodiment, the polycrystalline silicon pattern in areas other than the grooves is removed, leaving almost completely the polycrystalline silicon pattern in the grooves. Next, the silicon nitride film 16 and silicon oxide film 15 are etched using the patterned resist 25 as a mask (
Figure 2A).

Next, after covering the n-type well region with a resist 26,
For example, boron ions are implanted as a type impurity into the surface of the silicon substrate 1 to form a channel stopper layer 27 (FIG. 2B).

Next, oxidation is performed using the silicon nitride film 16 as a mask to form a silicon oxide film 28 on the surface of the polycrystalline silicon model in the trench and on the surface of the silicon substrate (FIG. 2C).

Hereinafter, by the method described in Example 1, a structure corresponding to FIG.

FIG. 3 shows a cross-sectional view of a semiconductor device at the main steps of a sixth embodiment of the present invention.

In the first embodiment, a silicon nitride film formed by ECR deposition was used as the third thin film covering the n-type well region.
Instead of this, a metal thin film such as aluminum or molybdenum can also be used.

After obtaining the structure shown in FIG. 1C according to the method described in the first embodiment, 29 is deposited on a thin metal such as aluminum or molybdenum by vapor deposition or sputtering. As shown in FIG. 3, by making the metal atoms fly almost perpendicularly to the silicon substrate 1, it is possible to prevent them from adhering to the side surfaces of the steps.

The resist 5 is removed using an organic solvent such as acetone, and the metal thin film 29 is lifted off to obtain the structure shown in FIG. 1E.

Next, after forming the groove 10 by the method described in the first embodiment, the silicon oxide film 4 is side-etched, boron ions are implanted, and a channel stopper layer 13 is formed at the top of one side of the groove and at the bottom of the groove. and 14 are formed, and the silicon oxide film 4 and metal thin film 29 are removed. When aluminum or molybdenum is used as the metal thin film 29, the metal thin film 29 can be easily removed using a mixed solution of sulfuric acid and hydrogen peroxide. High-temperature heat treatment to further diffuse the ions implanted into the well region is performed on the metal thin film 29.
This is done after removing the .

〔Effect of the invention〕

As explained above, according to the present invention, a channel stopper layer can be formed on one side of a trench around a well region using a self-alignment line, so semiconductor devices can be manufactured with high precision and high yield through a simple process. There are advantages that can be achieved.

Further, according to the present invention, since the channel stopper layer is formed only in a very limited region on the side surface of the groove, no shadow is exerted on the active region of the MOSFET.

[Brief explanation of drawings]

1A to 1J are process diagrams of the first embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional structures of a semiconductor device in main steps of the second embodiment of the present invention. 3 are cross-sectional structural diagrams of a semiconductor device in essential steps of a third embodiment of the present invention, and FIGS. 4A to 4C are process diagrams according to a conventional manufacturing method. 1... Silicon substrate, 2... Silicon oxide film,
3... Silicon nitride film, 4... Silicon oxide film as the first thin film, 5... Resist as the second thin film, 6... Well region, 7... As the third thin film silicon nitride pattern, 8... under-etched region, 9
...Il, @ silicon nitride on the side surface of the step where W is sparse,
10...Groove, 11...Side etched region, 12...
・Groove bottom, 15...Channel stopper layer on the groove side surface, 14
...Channel stopper layer at the bottom of the trench, 15...Silicon oxide film, 16...Silicon nitride film, 17...Polycrystalline silicon film as the fourth thin film filling the trench, 18...
・Silicon oxide film, 19... Gate oxide sliding door, 20...
・Gate electrode, 21...? Diffusion layer, 22...p+
Diffusion layer, 23... Interlayer insulating film, 24... Aluminum wiring, 25.26... Resist, 27... Channel stopper layer, 28... Silicon e-W, 29...
...metal thin film as the sixth thin film, 50...opening, 31...resist pattern,! +2: Boron ion implantation layer, 33: Resist pattern, 34: Phosphorus ion implantation layer, 35: Silicon oxide film frame, 36:
・Groove, 37...p single layer, 38...n single layer, 39・
...A career killer. Patent applicant Nippon Telegraph and Telephone Corporation agent Patent attorney Gobe Tamaichi (2 others) Third aspect of the present invention
Example of! Cross-sectional structural diagram of J part process 1 Fig. 3 32 Boron ion implantation layer 34jl ion S soil injection layer 3 1 layer 80-A- 39 Carrier killer 1 layer conventional cracking;

Claims (1)

[Claims] In a method for manufacturing a semiconductor device, a first thin film and a second thin film are formed on a main surface of a silicon substrate of one conductivity type in a region other than a region where a well of a conductivity type different from that of the silicon substrate is to be formed. forming a well by implanting ions of a conductivity type different from that of the silicon substrate into the silicon substrate using the second thin film as a mask; and forming a well using the second thin film as a mask. depositing a third thin film on the area where the well is to be formed and on the second thin film, and removing the second thin film to deposit a third thin film on the second thin film; Lifting off the third thin film; Forming a groove in the main surface of the silicon substrate using the under-etched first thin film and the third thin film as masks; etching the end face of the first thin film pattern and recessing the end face, and etching the same silicon substrate on the main surface of the silicon substrate and the bottom of the groove in the area where the end face of the first thin film pattern is side-etched. A method for manufacturing a semiconductor device, comprising the steps of: implanting conductive type ions; and burying a fourth thin film in the trench.