KR920022676A - 전자 플립-플롭 회로 - Google Patents
전자 플립-플롭 회로 Download PDFInfo
- Publication number
- KR920022676A KR920022676A KR1019920009109A KR920009109A KR920022676A KR 920022676 A KR920022676 A KR 920022676A KR 1019920009109 A KR1019920009109 A KR 1019920009109A KR 920009109 A KR920009109 A KR 920009109A KR 920022676 A KR920022676 A KR 920022676A
- Authority
- KR
- South Korea
- Prior art keywords
- storage element
- clock signal
- flop circuit
- input
- output
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0372—Bistable circuits of the master-slave type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
- H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 또 다른 공지된 전자 플립-플롭 회로도.
Claims (5)
- 데이타 입력, 데이타 출력 및 클럭 신호 입력을 구비하고 클럭 신호 제어하에서 데이타 입력에서 제1 저장 소자의 입력으로 데이타를 전달하고 상기 클럭 신호에 의해 직접 구동되는 제1 전달 게이트, 클럭 신호의 제어하에서 제1 저장 소자의 출력으로부터 제2 조정 소자의 입력-제2 저장 소자의 출력은 데이타 출력을 구성한다-으로 데이타를 전달하고 상기 클럭 신호에 의해 직접 구동되는 제2 전달 게이트를 구비하는 전자 플립-플롭 회로에 있어서, 제2 전달 게이트가 제1 저장 소자로부터 제2 저장 소자로 데이타를 전달하는 시간을 지연시키는 수단을 구비하는 것을 특징으로 하는 전자 플립-플롭 회로.
- 제1항에 있어서, 상기 수단은 게이트들이 제1 저장 소자의 출력에 접속되고 드레인들이 제2 저장 소자의 입력에 접속되는 pMOS 트랜지스터 및 nMOS 트랜지스터를 구비하며, 상기 pMOS 트랜지스터의 소스는 소자가 공급 전압원에 접속되는 게이트가 클럭 신호에 접속되는 추가 pMOS 트랜지스터의 드레인에 접속되고 nMOS 트랜지스터의 소스는 소스가 클럭 신호에 접속되는 추가 nMOS 트랜지스터의 드레인 및 게이트에 접속되는 것을 특징으로 하는 전자 플립-플롭 회로.
- 제1항 또는 2항에 있어서, 추가 반전 소자가 제2 저장 소자의 출력에 접속되는 것을 특징으로 하는 전자 플립-플롭 회로.
- 제1항 내지 3항에 있어서, 추가 반전 소자가 클럭 신호 입력에 접속되는 것을 특징으로 하는 전자 플립-플롭 회로.
- 제1항 내지 4항중 어느 한 항에 따르는 전자 플립-플롭 회로를 구비하는 집적 회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP91201316.6 | 1991-05-31 | ||
EP91201316 | 1991-05-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920022676A true KR920022676A (ko) | 1992-12-19 |
KR100239099B1 KR100239099B1 (ko) | 2000-01-15 |
Family
ID=8207681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920009109A KR100239099B1 (ko) | 1991-05-31 | 1992-05-28 | 전자 플립-플롭 회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5264738A (ko) |
JP (1) | JPH05160681A (ko) |
KR (1) | KR100239099B1 (ko) |
DE (1) | DE69229696T2 (ko) |
TW (1) | TW198159B (ko) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2764360B2 (ja) * | 1992-05-18 | 1998-06-11 | 三菱電機株式会社 | 並/直列変換回路、直/並列変換回路およびそれらを含むシステム |
JPH07183771A (ja) * | 1993-12-22 | 1995-07-21 | Fujitsu Ltd | フリップフロップ回路 |
US5467038A (en) * | 1994-02-15 | 1995-11-14 | Hewlett-Packard Company | Quick resolving latch |
EP0691741B1 (en) * | 1994-07-05 | 2004-10-06 | Matsushita Electric Industrial Co., Ltd. | Latch circuit |
EP0713292A3 (en) * | 1994-11-21 | 1997-10-01 | Motorola Inc | Feedback interlock circuit and its operating method |
US5684422A (en) * | 1995-01-25 | 1997-11-04 | Advanced Micro Devices, Inc. | Pipelined microprocessor including a high speed single-clock latch circuit |
US5789956A (en) * | 1995-05-26 | 1998-08-04 | Texas Instruments Incorporated | Low power flip-flop |
US5656953A (en) * | 1995-05-31 | 1997-08-12 | Texas Instruments Incorporated | Low overhead memory designs for IC terminals |
US5654660A (en) * | 1995-09-27 | 1997-08-05 | Hewlett-Packard Company | Level shifted high impedance input multiplexor |
KR100466457B1 (ko) * | 1995-11-08 | 2005-06-16 | 마츠시타 덴끼 산교 가부시키가이샤 | 신호전송회로,신호수신회로및신호송수신회로,신호전송방법,신호수신방법및신호송수신방법과반도체집적회로및그제어방법 |
JP3382144B2 (ja) * | 1998-01-29 | 2003-03-04 | 株式会社東芝 | 半導体集積回路装置 |
US6188260B1 (en) * | 1999-01-22 | 2001-02-13 | Agilent Technologies | Master-slave flip-flop and method |
JP2000286696A (ja) * | 1999-03-30 | 2000-10-13 | Mitsubishi Electric Corp | 分周回路 |
US20020000858A1 (en) | 1999-10-14 | 2002-01-03 | Shih-Lien L. Lu | Flip-flop circuit |
DE10163884A1 (de) * | 2001-12-22 | 2003-07-10 | Henkel Kgaa | Neue Alkalische Protease aus Bacillus sp. (DSM 14392) und Wasch- und Reinigungsmittel enthaltend diese neue Alkalische Protease |
US6901570B2 (en) | 2002-03-12 | 2005-05-31 | International Business Machines Corporation | Method of generating optimum skew corners for a compact device model |
JP4130329B2 (ja) * | 2002-04-18 | 2008-08-06 | 松下電器産業株式会社 | スキャンパス回路および当該スキャンパス回路を備えた半導体集積回路 |
US7091742B2 (en) * | 2002-12-19 | 2006-08-15 | Tellabs Operations, Inc. | Fast ring-out digital storage circuit |
US6831494B1 (en) | 2003-05-16 | 2004-12-14 | Transmeta Corporation | Voltage compensated integrated circuits |
JP4279620B2 (ja) * | 2003-07-11 | 2009-06-17 | Okiセミコンダクタ株式会社 | レベルシフト回路 |
DE102004008757B4 (de) * | 2004-02-23 | 2006-04-06 | Infineon Technologies Ag | Paritätsprüfungs-Schaltung zur kontinuierlichen Prüfung der Parität einer Speicherzelle |
US7142018B2 (en) | 2004-06-08 | 2006-11-28 | Transmeta Corporation | Circuits and methods for detecting and assisting wire transitions |
US7405597B1 (en) | 2005-06-30 | 2008-07-29 | Transmeta Corporation | Advanced repeater with duty cycle adjustment |
US7498846B1 (en) | 2004-06-08 | 2009-03-03 | Transmeta Corporation | Power efficient multiplexer |
US7336103B1 (en) | 2004-06-08 | 2008-02-26 | Transmeta Corporation | Stacked inverter delay chain |
US7635992B1 (en) | 2004-06-08 | 2009-12-22 | Robert Paul Masleid | Configurable tapered delay chain with multiple sizes of delay elements |
US7173455B2 (en) | 2004-06-08 | 2007-02-06 | Transmeta Corporation | Repeater circuit having different operating and reset voltage ranges, and methods thereof |
US7304503B2 (en) * | 2004-06-08 | 2007-12-04 | Transmeta Corporation | Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability |
US7656212B1 (en) | 2004-06-08 | 2010-02-02 | Robert Paul Masleid | Configurable delay chain with switching control for tail delay elements |
US7071747B1 (en) | 2004-06-15 | 2006-07-04 | Transmeta Corporation | Inverting zipper repeater circuit |
US7330080B1 (en) | 2004-11-04 | 2008-02-12 | Transmeta Corporation | Ring based impedance control of an output driver |
US7592842B2 (en) * | 2004-12-23 | 2009-09-22 | Robert Paul Masleid | Configurable delay chain with stacked inverter delay elements |
US7634749B1 (en) * | 2005-04-01 | 2009-12-15 | Cadence Design Systems, Inc. | Skew insensitive clocking method and apparatus |
JP5086993B2 (ja) | 2005-06-01 | 2012-11-28 | テクラテック・アクティーゼルスカブ | 複数の回路にタイミング信号を提供するための方法及び装置、集積回路並びにノード |
US20070013425A1 (en) * | 2005-06-30 | 2007-01-18 | Burr James B | Lower minimum retention voltage storage elements |
US7663408B2 (en) * | 2005-06-30 | 2010-02-16 | Robert Paul Masleid | Scannable dynamic circuit latch |
US7394681B1 (en) | 2005-11-14 | 2008-07-01 | Transmeta Corporation | Column select multiplexer circuit for a domino random access memory array |
US7642866B1 (en) | 2005-12-30 | 2010-01-05 | Robert Masleid | Circuits, systems and methods relating to a dynamic dual domino ring oscillator |
US7414485B1 (en) | 2005-12-30 | 2008-08-19 | Transmeta Corporation | Circuits, systems and methods relating to dynamic ring oscillators |
US8067970B2 (en) * | 2006-03-31 | 2011-11-29 | Masleid Robert P | Multi-write memory circuit with a data input and a clock input |
US7710153B1 (en) * | 2006-06-30 | 2010-05-04 | Masleid Robert P | Cross point switch |
US7495466B1 (en) | 2006-06-30 | 2009-02-24 | Transmeta Corporation | Triple latch flip flop system and method |
US7995618B1 (en) * | 2007-10-01 | 2011-08-09 | Teklatech A/S | System and a method of transmitting data from a first device to a second device |
US9985611B2 (en) * | 2015-10-23 | 2018-05-29 | Intel Corporation | Tunnel field-effect transistor (TFET) based high-density and low-power sequential |
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US4473760A (en) * | 1982-12-13 | 1984-09-25 | Western Digital Corporation | Fast digital sample resolution circuit |
US4663546A (en) * | 1986-02-20 | 1987-05-05 | Motorola, Inc. | Two state synchronizer |
US4929850A (en) * | 1987-09-17 | 1990-05-29 | Texas Instruments Incorporated | Metastable resistant flip-flop |
JPH0229124A (ja) * | 1988-07-19 | 1990-01-31 | Toshiba Corp | スタンダードセル |
JP2621993B2 (ja) * | 1989-09-05 | 1997-06-18 | 株式会社東芝 | フリップフロップ回路 |
US5132577A (en) * | 1991-04-11 | 1992-07-21 | National Semiconductor Corporation | High speed passgate, latch and flip-flop circuits |
-
1992
- 1992-04-25 TW TW081103256A patent/TW198159B/zh active
- 1992-05-22 DE DE69229696T patent/DE69229696T2/de not_active Expired - Fee Related
- 1992-05-28 KR KR1019920009109A patent/KR100239099B1/ko not_active IP Right Cessation
- 1992-05-29 US US07/891,314 patent/US5264738A/en not_active Expired - Fee Related
- 1992-05-29 JP JP4138711A patent/JPH05160681A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH05160681A (ja) | 1993-06-25 |
DE69229696T2 (de) | 2000-02-17 |
KR100239099B1 (ko) | 2000-01-15 |
US5264738A (en) | 1993-11-23 |
DE69229696D1 (de) | 1999-09-09 |
TW198159B (ko) | 1993-01-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |