KR920022676A - 전자 플립-플롭 회로 - Google Patents

전자 플립-플롭 회로 Download PDF

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Publication number
KR920022676A
KR920022676A KR1019920009109A KR920009109A KR920022676A KR 920022676 A KR920022676 A KR 920022676A KR 1019920009109 A KR1019920009109 A KR 1019920009109A KR 920009109 A KR920009109 A KR 920009109A KR 920022676 A KR920022676 A KR 920022676A
Authority
KR
South Korea
Prior art keywords
storage element
clock signal
flop circuit
input
output
Prior art date
Application number
KR1019920009109A
Other languages
English (en)
Other versions
KR100239099B1 (ko
Inventor
요세피우스 마리아 벤드릭 헨드리쿠스
안토니우스 요한네스 마리아 반 덴 엘슈트 안드레아스
마리누스 후이저 코르넬리스
Original Assignee
프레데릭 얀 스미트
엔.브이.필립스 글로아이람펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프레데릭 얀 스미트, 엔.브이.필립스 글로아이람펜파브리켄 filed Critical 프레데릭 얀 스미트
Publication of KR920022676A publication Critical patent/KR920022676A/ko
Application granted granted Critical
Publication of KR100239099B1 publication Critical patent/KR100239099B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음.

Description

전자 플립-플롭 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 또 다른 공지된 전자 플립-플롭 회로도.

Claims (5)

  1. 데이타 입력, 데이타 출력 및 클럭 신호 입력을 구비하고 클럭 신호 제어하에서 데이타 입력에서 제1 저장 소자의 입력으로 데이타를 전달하고 상기 클럭 신호에 의해 직접 구동되는 제1 전달 게이트, 클럭 신호의 제어하에서 제1 저장 소자의 출력으로부터 제2 조정 소자의 입력-제2 저장 소자의 출력은 데이타 출력을 구성한다-으로 데이타를 전달하고 상기 클럭 신호에 의해 직접 구동되는 제2 전달 게이트를 구비하는 전자 플립-플롭 회로에 있어서, 제2 전달 게이트가 제1 저장 소자로부터 제2 저장 소자로 데이타를 전달하는 시간을 지연시키는 수단을 구비하는 것을 특징으로 하는 전자 플립-플롭 회로.
  2. 제1항에 있어서, 상기 수단은 게이트들이 제1 저장 소자의 출력에 접속되고 드레인들이 제2 저장 소자의 입력에 접속되는 pMOS 트랜지스터 및 nMOS 트랜지스터를 구비하며, 상기 pMOS 트랜지스터의 소스는 소자가 공급 전압원에 접속되는 게이트가 클럭 신호에 접속되는 추가 pMOS 트랜지스터의 드레인에 접속되고 nMOS 트랜지스터의 소스는 소스가 클럭 신호에 접속되는 추가 nMOS 트랜지스터의 드레인 및 게이트에 접속되는 것을 특징으로 하는 전자 플립-플롭 회로.
  3. 제1항 또는 2항에 있어서, 추가 반전 소자가 제2 저장 소자의 출력에 접속되는 것을 특징으로 하는 전자 플립-플롭 회로.
  4. 제1항 내지 3항에 있어서, 추가 반전 소자가 클럭 신호 입력에 접속되는 것을 특징으로 하는 전자 플립-플롭 회로.
  5. 제1항 내지 4항중 어느 한 항에 따르는 전자 플립-플롭 회로를 구비하는 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920009109A 1991-05-31 1992-05-28 전자 플립-플롭 회로 KR100239099B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP91201316 1991-05-31
EP91201316.6 1991-05-31

Publications (2)

Publication Number Publication Date
KR920022676A true KR920022676A (ko) 1992-12-19
KR100239099B1 KR100239099B1 (ko) 2000-01-15

Family

ID=8207681

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920009109A KR100239099B1 (ko) 1991-05-31 1992-05-28 전자 플립-플롭 회로

Country Status (5)

Country Link
US (1) US5264738A (ko)
JP (1) JPH05160681A (ko)
KR (1) KR100239099B1 (ko)
DE (1) DE69229696T2 (ko)
TW (1) TW198159B (ko)

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US6188260B1 (en) * 1999-01-22 2001-02-13 Agilent Technologies Master-slave flip-flop and method
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Also Published As

Publication number Publication date
DE69229696D1 (de) 1999-09-09
DE69229696T2 (de) 2000-02-17
JPH05160681A (ja) 1993-06-25
US5264738A (en) 1993-11-23
KR100239099B1 (ko) 2000-01-15
TW198159B (ko) 1993-01-11

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