KR920013711A - 반도체 집적회로장치 - Google Patents

반도체 집적회로장치 Download PDF

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Publication number
KR920013711A
KR920013711A KR1019910022528A KR910022528A KR920013711A KR 920013711 A KR920013711 A KR 920013711A KR 1019910022528 A KR1019910022528 A KR 1019910022528A KR 910022528 A KR910022528 A KR 910022528A KR 920013711 A KR920013711 A KR 920013711A
Authority
KR
South Korea
Prior art keywords
mos transistor
data
integrated circuit
semiconductor integrated
circuit device
Prior art date
Application number
KR1019910022528A
Other languages
English (en)
Other versions
KR960000715B1 (ko
Inventor
아츠시 스에오카
가츠시 나가바
히로유키 고이누마
Original Assignee
아오이 죠이치
가부시기가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시기가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR920013711A publication Critical patent/KR920013711A/ko
Application granted granted Critical
Publication of KR960000715B1 publication Critical patent/KR960000715B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 집적회로장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예를 도시하 블록도, 제2도는 제1실시예의 동작을 설명하기 위한 타임챠트, 제3도는 제2실시예에 관한 강압회로를 도시하는 블록도.

Claims (1)

  1. 데이타 유지노드와, 소정의 전위로 프리차지된 데이타선(BLO)과, 소스, 드레인을 상기 데이타선, 상기 데이타 유지 노드에 각각 접속한 MOS트랜지스터(TMO)와, 이 MOS트랜지스터를 개재하고 상기 데이타선에 전송된 데이타를 증폭하는 센스앰프(SA)와, 상기 MOS트랜지스터의 게이트에 절대치로 비료하여 드레인 전압 이상인 전압을 부여하는 승압회로(WLDV)와, 상기 센스 앰프의 활성화의 타이밍으로 상기 MOS트랜지스터의 게이트 저압의 절대치를 작게하는 수단(DWN)을 구비하는 것을 특징으로 하는 반도체 집적회로 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910022528A 1990-12-13 1991-12-10 반도체 집적회로장치 KR960000715B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2402053A JP2823361B2 (ja) 1990-12-13 1990-12-13 半導体集積回路装置
JP90-402053 1990-12-13

Publications (2)

Publication Number Publication Date
KR920013711A true KR920013711A (ko) 1992-07-29
KR960000715B1 KR960000715B1 (ko) 1996-01-11

Family

ID=18511861

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910022528A KR960000715B1 (ko) 1990-12-13 1991-12-10 반도체 집적회로장치

Country Status (3)

Country Link
US (1) US5274592A (ko)
JP (1) JP2823361B2 (ko)
KR (1) KR960000715B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NZ224999A (en) * 1987-06-16 1990-10-26 Comalco Alu Aluminium alloy suitable for sacrificial anodes
US5724286A (en) * 1994-12-14 1998-03-03 Mosaid Technologies Incorporated Flexible DRAM array
US6483139B1 (en) 2001-07-05 2002-11-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device formed on semiconductor substrate
JP2013004136A (ja) * 2011-06-15 2013-01-07 Elpida Memory Inc 半導体装置
US11205470B2 (en) * 2020-04-20 2021-12-21 Micron Technology, Inc. Apparatuses and methods for providing main word line signal with dynamic well
US11990175B2 (en) 2022-04-01 2024-05-21 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0061289B1 (en) * 1981-03-17 1988-07-27 Hitachi, Ltd. Dynamic type semiconductor monolithic memory
JPH0787034B2 (ja) * 1984-05-07 1995-09-20 株式会社日立製作所 半導体集積回路装置
US4896297A (en) * 1987-10-23 1990-01-23 Mitsubishi Denki Kabushiki Kaisha Circuit for generating a boosted signal for a word line
JP2644261B2 (ja) * 1988-03-15 1997-08-25 株式会社東芝 ダイナミック型半導体記憶装置
JPH02247892A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd ダイナミックランダムアクセスメモリ
US5075890A (en) * 1989-05-02 1991-12-24 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with nand cell
JPH0383371A (ja) * 1989-08-28 1991-04-09 Mitsubishi Electric Corp 不揮発性半導体記憶装置の昇圧回路
JP2704459B2 (ja) * 1989-10-21 1998-01-26 松下電子工業株式会社 半導体集積回路装置
JP2778199B2 (ja) * 1990-04-27 1998-07-23 日本電気株式会社 内部降圧回路

Also Published As

Publication number Publication date
JPH04214291A (ja) 1992-08-05
US5274592A (en) 1993-12-28
JP2823361B2 (ja) 1998-11-11
KR960000715B1 (ko) 1996-01-11

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