KR920020684A - 리이드 프레임 및 그 제조방법 - Google Patents

리이드 프레임 및 그 제조방법 Download PDF

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Publication number
KR920020684A
KR920020684A KR1019920005273A KR920005273A KR920020684A KR 920020684 A KR920020684 A KR 920020684A KR 1019920005273 A KR1019920005273 A KR 1019920005273A KR 920005273 A KR920005273 A KR 920005273A KR 920020684 A KR920020684 A KR 920020684A
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KR
South Korea
Prior art keywords
lead frame
manufacturing
etching
groove
frame material
Prior art date
Application number
KR1019920005273A
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English (en)
Inventor
데쓰야 오오쓰끼
Original Assignee
아이자와 스스무
세이꼬오 에뿌손 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아이자와 스스무, 세이꼬오 에뿌손 가부시기가이샤 filed Critical 아이자와 스스무
Publication of KR920020684A publication Critical patent/KR920020684A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음

Description

리이드 프레임 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 관한 리이드 프레임의 제조방법의 실시예의 설명도.
제2도는 본 발명에 관한 리이드 프레임의 다른 실시예의 설명도.
제3도-제13도는 본 발명에 관한 리이드 프레임 제조방법의 다른 실시예의 설명도.

Claims (6)

  1. 반도체소자를 탑재하는 다이패드와 와이어로 반도체 소자의 전극과 각기 접속하는 다수의 이너리이드 등을 구비하여 이너리이드를 2회 또는 그 이상의 사진 평판 기술에 의한 에칭 그렇지 않으면 프레스 가공 또는 이것들의 조합으로 헝성한 것을 특징으로 하는 리이드 프레임.
  2. 반도체소자를 탑재하는 다이패드와 와이어로 반도체 소자의 전극과 각기 접속하는 다수의 이너리이드 등으로 된 리이드 프레임을 리이드 프레임 소재로 부터 제조하는 공정에 있어서, 2회 또는 그 이상의 사진 평판 기술에 의한 에칭 그렇지 않으면 프레스 가공 또는 이것들의 조합으로 이너리이드를 형성하는 것을 특징으로 하는 리이드프레임의 제조방법.
  3. 제2항에 있어서, 리이드 프레임 소재의 양면으로부터 각기 에칭함에 따라 저부가 서로 겹치도록 홈을 형성하는 것을 특징으로 하는 리이드 프레임의 제조방법.
  4. 제2항에 있어서, 리이드 프레임 소재의 한쪽면에 에칭함에 따라 홈을 형성하고 이어서 에칭 또는 프레스 가공함에 따라 홈의 저부로 부터 다른쪽면으로 도달하는 슬릿을 형성하는 것을 특징으로 하는 리이드 프레임의 제조방법.
  5. 제2항에 있어서, 리이드 프레임소재의 양면으로 부터 에칭함에 따라 저부가 서로 간섭하지 않도록 홈을 형성하고, 이어서 이것을 양홈의 저부사이를 에칭 또는 프레스 가공에 의한 슬릿으로 연결하는 것을 특징으로 하는 리이드 프레임의 제조방법.
  6. 제2항에 있어서, 리이드 프레임소재의 한쪽면으로부터 프레스 가공함에 따라 두께의 대략 2분의 1의 깊이의 홈을 형성하고 이어서 에칭 또는 프레스 가공함에 따라 홈의 저부로 부터 다른쪽면으로 도달하는 슬릿을 형성하는 것을 특징으로 하는 리이드 프레임의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920005273A 1991-04-03 1992-03-30 리이드 프레임 및 그 제조방법 KR920020684A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-71132 1991-04-03
JP3071132A JP3018542B2 (ja) 1991-04-03 1991-04-03 リードフレーム及びその製造方法

Publications (1)

Publication Number Publication Date
KR920020684A true KR920020684A (ko) 1992-11-21

Family

ID=13451747

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920005273A KR920020684A (ko) 1991-04-03 1992-03-30 리이드 프레임 및 그 제조방법

Country Status (3)

Country Link
US (1) US5230144A (ko)
JP (1) JP3018542B2 (ko)
KR (1) KR920020684A (ko)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06275764A (ja) * 1993-03-19 1994-09-30 Fujitsu Miyagi Electron:Kk リードフレーム及びそのリードフレームを用いた半導体装置の製造方法
US6361959B1 (en) 1994-07-07 2002-03-26 Tessera, Inc. Microelectronic unit forming methods and materials
US6117694A (en) * 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US6828668B2 (en) * 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
JP3257904B2 (ja) * 1994-08-11 2002-02-18 新光電気工業株式会社 リードフレームとその製造方法
US5629239A (en) * 1995-03-21 1997-05-13 Tessera, Inc. Manufacture of semiconductor connection components with frangible lead sections
US5966592A (en) 1995-11-21 1999-10-12 Tessera, Inc. Structure and method for making a compliant lead for a microelectronic device
US6429050B1 (en) * 1997-12-18 2002-08-06 Texas Instruments Incorporated Fine pitch lead frame and method
US6465744B2 (en) 1998-03-27 2002-10-15 Tessera, Inc. Graded metallic leads for connection to microelectronic elements
US6274822B1 (en) 1998-03-27 2001-08-14 Tessera, Inc. Manufacture of semiconductor connection components with frangible lead sections
US6309910B1 (en) 1998-05-18 2001-10-30 Tessera Inc. Microelectronic components with frangible lead sections
TW498443B (en) * 2001-06-21 2002-08-11 Advanced Semiconductor Eng Singulation method for manufacturing multiple lead-free semiconductor packages
JP2003258183A (ja) * 2002-03-04 2003-09-12 Shinko Electric Ind Co Ltd リードフレームの製造方法
MY136216A (en) * 2004-02-13 2008-08-29 Semiconductor Components Ind Method of forming a leadframe for a semiconductor package
JP4270282B2 (ja) 2007-01-23 2009-05-27 セイコーエプソン株式会社 半導体装置の製造方法
JP5120037B2 (ja) * 2008-04-10 2013-01-16 住友金属鉱山株式会社 リード露出型パッケージ用リードフレーム
JP5443497B2 (ja) * 2008-09-25 2014-03-19 エルジー イノテック カンパニー リミテッド リードフレームの製造方法
JP5304431B2 (ja) * 2009-05-19 2013-10-02 凸版印刷株式会社 リードフレーム及びその製造方法及びそれを用いた半導体発光装置
JP5304314B2 (ja) * 2008-11-07 2013-10-02 凸版印刷株式会社 Ｌｅｄ発光素子用リードフレーム及びその製造方法及びそれを用いたｌｅｄ発光素子
JP5453642B2 (ja) * 2009-02-20 2014-03-26 Ｓｈマテリアル株式会社 リードフレームの製造方法
US20110108966A1 (en) * 2009-11-11 2011-05-12 Henry Descalzo Bathan Integrated circuit packaging system with concave trenches and method of manufacture thereof
JP5678727B2 (ja) 2011-03-03 2015-03-04 セイコーエプソン株式会社 振動デバイス、振動デバイスの製造方法、電子機器
JP6150469B2 (ja) * 2012-07-12 2017-06-21 株式会社三井ハイテック リードフレームの製造方法
JP6788825B2 (ja) * 2016-07-20 2020-11-25 大日本印刷株式会社 リードフレームおよび半導体装置
US10497602B2 (en) 2016-08-01 2019-12-03 Semiconductor Components Industries, Llc Process of forming an electronic device including forming an electronic component and removing a portion of a substrate
JP2017092500A (ja) * 2017-02-15 2017-05-25 大日本印刷株式会社 Ｌｅｄ用リードフレーム、光半導体装置、およびｌｅｄ用リードフレームの製造方法
TWI676252B (zh) * 2018-07-23 2019-11-01 長華科技股份有限公司 導線架及其製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5824020B2 (ja) * 1979-12-13 1983-05-18 株式会社東芝 半導体装置
JPS5987845A (ja) * 1982-11-10 1984-05-21 Toppan Printing Co Ltd リ−ドフレ−ムの製造方法
JPS63128739A (ja) * 1986-11-19 1988-06-01 Nec Corp リ−ドフレ−ムの製造方法
JPH02209355A (ja) * 1989-02-09 1990-08-20 Yokohama Rubber Co Ltd:The 巻物自動掛替え方法
JPH02244663A (ja) * 1989-03-16 1990-09-28 Toppan Printing Co Ltd リードフレームの製造方法
JPH02284453A (ja) * 1989-04-26 1990-11-21 Toppan Printing Co Ltd 半導体集積回路用リードフレームの製造方法
JPH036048A (ja) * 1989-06-02 1991-01-11 Toppan Printing Co Ltd リードフレーム及びその製造方法

Also Published As

Publication number Publication date
JPH04306867A (ja) 1992-10-29
JP3018542B2 (ja) 2000-03-13
US5230144A (en) 1993-07-27

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