JPS5683959A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5683959A
JPS5683959A JP16082679A JP16082679A JPS5683959A JP S5683959 A JPS5683959 A JP S5683959A JP 16082679 A JP16082679 A JP 16082679A JP 16082679 A JP16082679 A JP 16082679A JP S5683959 A JPS5683959 A JP S5683959A
Authority
JP
Japan
Prior art keywords
width
main surface
lead
bonding
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16082679A
Other languages
Japanese (ja)
Other versions
JPS5824020B2 (en
Inventor
Yoshimasa Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54160826A priority Critical patent/JPS5824020B2/en
Publication of JPS5683959A publication Critical patent/JPS5683959A/en
Publication of JPS5824020B2 publication Critical patent/JPS5824020B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase a bonding efficiency without contact of a wire to an adjacent lead by a method wherein shapes of top ends of inner-leads which form a lead frame are made broader in width for surfaces where wire-bondings are applied and narrower in width for the reverse. CONSTITUTION:A sectional shape of the inner-lead 11 forming the lead frame should be made as follows. That is, the width of one main surface 12 applied a wire bonding is made a predetermined one necessary for the bonding and the other main surface 13 facing thereto is made narrower in width that the former. Thus, the broadest width W comes at the position near the main surface 12 and the cutout width is also made narrower than the half of a thickness (t) of the lead on the main surface 12 side. This is accomplished by the application of an ordinary etching. Whereby the distance between the leads 11 adjacent to each other becomes broader, the bonding efficiency is improved and if necessary, the frame can be made small corresponding to making pellets small-size.
JP54160826A 1979-12-13 1979-12-13 semiconductor equipment Expired JPS5824020B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54160826A JPS5824020B2 (en) 1979-12-13 1979-12-13 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54160826A JPS5824020B2 (en) 1979-12-13 1979-12-13 semiconductor equipment

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP59007074A Division JPS59150439A (en) 1984-01-20 1984-01-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5683959A true JPS5683959A (en) 1981-07-08
JPS5824020B2 JPS5824020B2 (en) 1983-05-18

Family

ID=15723238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54160826A Expired JPS5824020B2 (en) 1979-12-13 1979-12-13 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5824020B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230144A (en) * 1991-04-03 1993-07-27 Seiko Epson Corporation Method of producing lead frame
US7105378B2 (en) * 2004-02-13 2006-09-12 Semiconductor Components Industries, Llc Method of forming a leadframe for a semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230144A (en) * 1991-04-03 1993-07-27 Seiko Epson Corporation Method of producing lead frame
US7105378B2 (en) * 2004-02-13 2006-09-12 Semiconductor Components Industries, Llc Method of forming a leadframe for a semiconductor package

Also Published As

Publication number Publication date
JPS5824020B2 (en) 1983-05-18

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