JPS5726454A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the stepwise difference on the surface of a chip by disposing the side edge of one wire within the width of the other wire or so disposing as not to have common region on the planar surface at the part parallel to the same lattice axis of the wires of the adjacent wiring layers. CONSTITUTION:The side edge 19 of the first layer wire 7' is disposed within the width of the second layer wire 8' on a lattice axis 2' at the side edge 19 at the part on which the first wire 7' is laid in X-direction. Thus, the stepwise difference between the first layer and the second layer is displaced one another in the section 10-10', and since the size of the difference becomes two steps of d1=M1+IM1- It2, d2=M2+IM2-It2 as shown, the insulating film of the side face of the step does not become thin, nor the third layer wire becomes thin at the difference. Or the parallel wires on the same lattice wire may be entirely removed without common wire. According to this configuration the stepwise difference can be prevented on the surface of the chip without losing the advantages of the common wire lattice axis on the entire wiring layer.