JPS56137664A - Lead frame and semiconductor device having lead frame - Google Patents

Lead frame and semiconductor device having lead frame

Info

Publication number
JPS56137664A
JPS56137664A JP4049180A JP4049180A JPS56137664A JP S56137664 A JPS56137664 A JP S56137664A JP 4049180 A JP4049180 A JP 4049180A JP 4049180 A JP4049180 A JP 4049180A JP S56137664 A JPS56137664 A JP S56137664A
Authority
JP
Japan
Prior art keywords
lead
lead frame
thickness
constitution
smaller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4049180A
Other languages
Japanese (ja)
Inventor
Michiaki Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP4049180A priority Critical patent/JPS56137664A/en
Publication of JPS56137664A publication Critical patent/JPS56137664A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To arrange so that a lead width and a lead-to-lead pitch may be reduced by forming the thickness of an inner lead smaller than that of an outer lead. CONSTITUTION:A high-density semiconductor element 7 is fixed inside a central concave part of a ceramic base 5 and a lead frame 9 is adhered through melting on the peripery of the base 3 using an adhesive 8. Wire 13 is bonded each between an inner lead 10 and an element electrode 12. The lead frame 9 and the inner lead 10 are formed in a monoblock as a single piece. When the leads 10, 11 are formed, the sheet thickness t1 of the lead 10 is formed in such manner that it is smaller than the sheet thickness to of the lead 11. Under this constitution, it is possible to make possible press processing or etching process in a delicate manner by virtue of reduced thickness. Thus the width of the lead 10 and a lead-to-lead pitch can be minimized.
JP4049180A 1980-03-31 1980-03-31 Lead frame and semiconductor device having lead frame Pending JPS56137664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4049180A JPS56137664A (en) 1980-03-31 1980-03-31 Lead frame and semiconductor device having lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4049180A JPS56137664A (en) 1980-03-31 1980-03-31 Lead frame and semiconductor device having lead frame

Publications (1)

Publication Number Publication Date
JPS56137664A true JPS56137664A (en) 1981-10-27

Family

ID=12582041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4049180A Pending JPS56137664A (en) 1980-03-31 1980-03-31 Lead frame and semiconductor device having lead frame

Country Status (1)

Country Link
JP (1) JPS56137664A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6248053A (en) * 1985-08-28 1987-03-02 Nec Corp Manufacture of lead frame for semiconductor device
US4891333A (en) * 1984-10-09 1990-01-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891333A (en) * 1984-10-09 1990-01-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
JPS6248053A (en) * 1985-08-28 1987-03-02 Nec Corp Manufacture of lead frame for semiconductor device

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