JPS5763837A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5763837A
JPS5763837A JP13937480A JP13937480A JPS5763837A JP S5763837 A JPS5763837 A JP S5763837A JP 13937480 A JP13937480 A JP 13937480A JP 13937480 A JP13937480 A JP 13937480A JP S5763837 A JPS5763837 A JP S5763837A
Authority
JP
Japan
Prior art keywords
metal layer
ohmic contact
substrate
semiconductor substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13937480A
Other languages
Japanese (ja)
Inventor
Toshihiro Suzuki
Haruo Yamagishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13937480A priority Critical patent/JPS5763837A/en
Publication of JPS5763837A publication Critical patent/JPS5763837A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain an excellent contact without damaging a semiconductor substrate of a III-V family by providing on the substrate an electrode prepared by laying the third metal layer Ta for preventing mutual diffusion intermediately between AuGe constituting an ohmic contact and Au having an excellent bonding property. CONSTITUTION:The electrode is formed by laying the first metal layer 12, the second metal layer 13, the third metal layer 14 and the fourth metal layer 15 sequentially on the GaAs semiconductor substrate 11. The first metal layer constitutes the ohmic contact with the substrate and is formed of AuGe. The fourth metal layer serves as a protection layer for the third metal layer in etching, being formed od Au. The third metal layer, preventing other elements from diffusing into the fourth metal layer, is formed of Ta. The second metal layer is a surface layer requiring bonding property, being formed of gold. By this constitution, the semiconductor device having the excellent ohmic contact is obtained without damaging the semiconductor substrate of a III-V family.
JP13937480A 1980-10-07 1980-10-07 Semiconductor device Pending JPS5763837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13937480A JPS5763837A (en) 1980-10-07 1980-10-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13937480A JPS5763837A (en) 1980-10-07 1980-10-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5763837A true JPS5763837A (en) 1982-04-17

Family

ID=15243830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13937480A Pending JPS5763837A (en) 1980-10-07 1980-10-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5763837A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222446A (en) * 1985-07-22 1987-01-30 Rohm Co Ltd Forming method of ohmic electrode
JPS6384125A (en) * 1986-09-29 1988-04-14 Nec Corp Method for forming electrode of compound semiconductor
US5422307A (en) * 1992-03-03 1995-06-06 Sumitomo Electric Industries, Ltd. Method of making an ohmic electrode using a TiW layer and an Au layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5464463A (en) * 1977-10-31 1979-05-24 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5464463A (en) * 1977-10-31 1979-05-24 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222446A (en) * 1985-07-22 1987-01-30 Rohm Co Ltd Forming method of ohmic electrode
JPS6384125A (en) * 1986-09-29 1988-04-14 Nec Corp Method for forming electrode of compound semiconductor
US5422307A (en) * 1992-03-03 1995-06-06 Sumitomo Electric Industries, Ltd. Method of making an ohmic electrode using a TiW layer and an Au layer

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