GB1267044A - - Google Patents

Info

Publication number
GB1267044A
GB1267044A GB1267044DA GB1267044A GB 1267044 A GB1267044 A GB 1267044A GB 1267044D A GB1267044D A GB 1267044DA GB 1267044 A GB1267044 A GB 1267044A
Authority
GB
United Kingdom
Prior art keywords
region
layer
window
type
shallow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1267044A publication Critical patent/GB1267044A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

1,267,044. Semi-conductor devices. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. 21 Aug., 1969 [31 Aug., 1968], No. 41738/69. Heading HlK. A shallow surface layer of a semi-conductor device is contacted by means of a deeper region of the same conductivity type which penetrates the shallow layer at its centre, an electrode being applied to the deeper region. An N type Si wafer (1) is masked with a silicon oxide or nitride layer (2), a window (3) is formed and boron is diffused-in to form a deep P type contact region 4. The window is enlarged and a second boron diffusion is used to form the shallow P type active region 6. A further insulating layer (8) is vapour deposited and a window (9) is formed above the contact region 4. A layer 10 of Ni covered with a layer 11 of Ag is vapour deposited to contact the P type region and parts of the metal layers overlying the insulating layer are removed together with the photoresist used in the etching of the window (9). A mound 12 of Ag is vapourdeposited or electrodeposited to contact layer 11 and overlie the insulating layer 8 to provide a large area bonding pad, Fig. 6. The impurity concentration of the deep region 4 is arranged to be less than that of region 6 so that the latter constitutes the active region of the device. In a modification, Fig. 7 (not shown), a second deep region (13) surrounds the edge of the shallow region. The semi-conductor device may be a diode or a transistor.
GB1267044D 1968-08-31 1969-08-21 Expired GB1267044A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19681764908 DE1764908B2 (en) 1968-08-31 1968-08-31 METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT

Publications (1)

Publication Number Publication Date
GB1267044A true GB1267044A (en) 1972-03-15

Family

ID=5698189

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1267044D Expired GB1267044A (en) 1968-08-31 1969-08-21

Country Status (2)

Country Link
DE (1) DE1764908B2 (en)
GB (1) GB1267044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2163597A (en) * 1984-08-21 1986-02-26 Ates Componenti Elettron Improvements in or relating to manufacture of semiconductor devices of high breakdown voltage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2163597A (en) * 1984-08-21 1986-02-26 Ates Componenti Elettron Improvements in or relating to manufacture of semiconductor devices of high breakdown voltage

Also Published As

Publication number Publication date
DE1764908A1 (en) 1971-07-01
DE1764908B2 (en) 1972-03-30

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees