JPS6444049A - Electrode for flip chip bonding - Google Patents

Electrode for flip chip bonding

Info

Publication number
JPS6444049A
JPS6444049A JP20133287A JP20133287A JPS6444049A JP S6444049 A JPS6444049 A JP S6444049A JP 20133287 A JP20133287 A JP 20133287A JP 20133287 A JP20133287 A JP 20133287A JP S6444049 A JPS6444049 A JP S6444049A
Authority
JP
Japan
Prior art keywords
layer
electrode
fusion
metal
bonding metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20133287A
Other languages
Japanese (ja)
Inventor
Hiroyuki Nobuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20133287A priority Critical patent/JPS6444049A/en
Publication of JPS6444049A publication Critical patent/JPS6444049A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13563Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565Only outside the bonding interface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent a fusion-bonding metal and a wiring layer from reacting by providing a barrier layer made of diffusion preventing metal or insulator of a fusion-bonding metal layer also on the side face of the metal. CONSTITUTION:An AuSn fusion-bonding metal layer 6 is formed as a bump through an Ni layer or a Pt/Ti layer as a barrier layer 5 made of the diffusion preventing metal of the fusion-bonding metal at an electrode forming position on an Au/AuGe ohmic contact electrode 3 formed on an N-type InP substrate 1. Then, an Ni layer 8 is deposited on a whole substrate, covered with an AZ resist, patterned to allow an AZ resist pattern 10 to remain on the periphery of the electrode. Thereafter, the pattern 10 is etched back by reactive ion etching using O2 to expose the layer 8 on the top of the electrode. Subsequently, the exposed layer 8 is removed by ion beam etching using Ar, and the pattern 10 is isolated. Thus, it can prevent the fusion-bonding metal from diffusing in or reacting with the ohmic contact electrode or the wiring electrode, thereby reducing preferable bonding and element characteristic deteriorations.
JP20133287A 1987-08-12 1987-08-12 Electrode for flip chip bonding Pending JPS6444049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20133287A JPS6444049A (en) 1987-08-12 1987-08-12 Electrode for flip chip bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20133287A JPS6444049A (en) 1987-08-12 1987-08-12 Electrode for flip chip bonding

Publications (1)

Publication Number Publication Date
JPS6444049A true JPS6444049A (en) 1989-02-16

Family

ID=16439260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20133287A Pending JPS6444049A (en) 1987-08-12 1987-08-12 Electrode for flip chip bonding

Country Status (1)

Country Link
JP (1) JPS6444049A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0923051A (en) * 1995-05-29 1997-01-21 Sgs Thomson Microelectron Sa Micromodule tobe used as surface mounting type package
US6958539B2 (en) * 2000-08-29 2005-10-25 Au Optronics Corporation Metal bump with an insulating sidewall and method of fabricating thereof
JP2007266531A (en) * 2006-03-30 2007-10-11 Oki Electric Ind Co Ltd Manufacturing method for semiconductor device
JP2009039719A (en) * 2003-05-14 2009-02-26 Sharper Image Corp Electrode self-cleaning mechanism with anti-arc guard for electro-kinetic air transporter-conditioner device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3066248A (en) * 1958-12-16 1962-11-27 Sarkes Tarzian Semiconductor device
JPS4732600U (en) * 1971-04-30 1972-12-12

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3066248A (en) * 1958-12-16 1962-11-27 Sarkes Tarzian Semiconductor device
JPS4732600U (en) * 1971-04-30 1972-12-12

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0923051A (en) * 1995-05-29 1997-01-21 Sgs Thomson Microelectron Sa Micromodule tobe used as surface mounting type package
US6958539B2 (en) * 2000-08-29 2005-10-25 Au Optronics Corporation Metal bump with an insulating sidewall and method of fabricating thereof
US7041589B2 (en) * 2000-08-29 2006-05-09 Au Optronics Corp. Metal bump with an insulating sidewall and method of fabricating thereof
JP2009039719A (en) * 2003-05-14 2009-02-26 Sharper Image Corp Electrode self-cleaning mechanism with anti-arc guard for electro-kinetic air transporter-conditioner device
JP2007266531A (en) * 2006-03-30 2007-10-11 Oki Electric Ind Co Ltd Manufacturing method for semiconductor device

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