JPS57153430A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57153430A JPS57153430A JP3846681A JP3846681A JPS57153430A JP S57153430 A JPS57153430 A JP S57153430A JP 3846681 A JP3846681 A JP 3846681A JP 3846681 A JP3846681 A JP 3846681A JP S57153430 A JPS57153430 A JP S57153430A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- electrode
- substrate
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 239000000758 substrate Substances 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
PURPOSE:To bring an interval between a gate electrode and an ohmic electrode to predetermined value by forming an Al film onto a substrate through a SiO2 film and shaping an opening with a desired shape to these films through the over-etching of the Al film when forming the gate electrode and the ohmic electrode of the semiconductor device. CONSTITUTION:An N type GaAs operating layer 12, the SiO2 film 21, the Al film 22 and a SiO2 film 24 are laminated onto the semi-insulating GaAs substrate 11, and a section except a region in which the gate electrode, a gate pad and wiring for plating the gate electrode are shaped is coated with a photo-resist film. The opening is formed through anisotropic dry etching to expose the substrate 11, a Schottky barrier gate electrode 51 is attached and coated with an Au film 52, and the film 24 is also coated with the Au film 52. A photo-resist film 41 is shaped to the surface while burying the opening, and only the electrode 51 and the Au film 52 protruded onto the electrode 51 in an eave shape are left onto the layer 12 through etching. P type source and drain regions 13 through the layer 12 are formed into the substrate 11 at both sides of the film 52, the film 52 is removed, and the electrodes 611, 612 are attached to a rerion 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3846681A JPS57153430A (en) | 1981-03-17 | 1981-03-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3846681A JPS57153430A (en) | 1981-03-17 | 1981-03-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57153430A true JPS57153430A (en) | 1982-09-22 |
Family
ID=12526018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3846681A Pending JPS57153430A (en) | 1981-03-17 | 1981-03-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57153430A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231040A (en) * | 1989-04-27 | 1993-07-27 | Mitsubishi Denki Kabushiki Kaisha | Method of making a field effect transistor |
| US5272095A (en) * | 1992-03-18 | 1993-12-21 | Research Triangle Institute | Method of manufacturing heterojunction transistors with self-aligned metal contacts |
-
1981
- 1981-03-17 JP JP3846681A patent/JPS57153430A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231040A (en) * | 1989-04-27 | 1993-07-27 | Mitsubishi Denki Kabushiki Kaisha | Method of making a field effect transistor |
| US5272095A (en) * | 1992-03-18 | 1993-12-21 | Research Triangle Institute | Method of manufacturing heterojunction transistors with self-aligned metal contacts |
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