JPH05267708A - Electrode structure for optical semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an electrode structure having a high reflectivity and low ohmic resistance against a compound semiconductor by a method wherein, after high melting point metal has been thinly deposited on the compound semiconductor in such a manner that it gives little effect on reflectivity, the metal having a high reflective factor is deposited. CONSTITUTION:An N-InP buffer layer 2, an N-InGaAs active layer 3 and an N-InP cap layer are grown respectively on an N-InP substrate using an MO-CVD method. After a pin junction has been formed by selectively diffusing (5) Zn on the above-mentioned epitaxial wafer, a hole with eaves is formed by Az resist which is treated by chlorobenzene, metal films of Ti, Ag, Zn and Ag are formed thereon by EB vapor-deposition under resistive heating. By preventing the alloy reaction between a high reflection metal and a semiconductor by providing a high melting point thin metal layer on the compound semiconductor, the decrease of reflection factor by alloying can be suppressed using the metal of high reflectivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a semiconductor device such as a PIN-photo diode (PD), an avalanche photo diode (APD) or the like.

[0002]

2. Description of the Related Art It is a well-known fact that in a back-illuminated type light receiving element, the reflected light from an electrode improves the quantum efficiency of the element. However, there is no electrode that has both low element resistance and high reflectance. For InP-based devices, gold-based materials (AuGe, AuZn, etc.) that are easy to obtain low ohmic contact are used. However, the gold system easily reacts with InP,
The reaction layer interferes with normal reflection. The interference is caused by non-uniformity of frequency characteristics due to absorption of light by the reaction layer and irregular reflection. The loss of light reflection of the former and the latter is very large, and normal reflection is AuZn / Ti / Pt.
When the / Au electrode was used, it was -20%, and the effect of improving the characteristics due to reflection was small, and there were problems of deterioration of pulse response characteristics due to irregular reflection and occurrence of non-uniformity of in-plane sensitivity.

[0003]

The response speed of the light receiving element is determined by the transit time of the carrier, the element capacitance, the parasitic capacitance, and the load resistance. Ultrafast (20GH _z) above becomes the carrier light absorbing layer from the running time issues must be thin, lowering of the quantum efficiency becomes a problem. Therefore, it is effective to use a structure in which the light that has once transmitted is reflected by the electrodes and reused.However, since the current electrodes form an alloy layer of a metal and a semiconductor to form a contact, unevenness of the interface or Due to absorption and irregular reflection of the alloy layer, there are problems such as small contribution to quantum efficiency and deterioration of pulse response characteristics at ultra-high speed.

[0004]

In order to solve the above-mentioned problems, in the first embodiment of the present invention, as an electrode of a light receiving element or the like, a thin refractory metal is thinly formed on a compound semiconductor within a range in which reflectance is little affected. The problem is solved by depositing a metal having a high reflectance (which is easily alloyed with the compound semiconductor) after depositing. As a solution to the problem of ohmic property, Zn
It suffices to have a layered structure in which the compound semiconductor surface is doped with, etc., and when used as a reflective film, the alloy reaction speed with the compound semiconductor is low, and a metal with high reflectance is required.
For this, a structure in which the above impurities are not doped can be used.

Specifically, on a semiconductor layer of an optical semiconductor device, a refractory metal layer is used as a first layer and Ag, A are used as a second layer.
The first layer is a Zn, Ge layer as the third layer, and the fourth layer is Ag or A
1 layer is formed, and Ag or Al of the second layer, Zn of the third layer and Ag or Al of the fourth layer are alloyed to form AgZn or Al.
An optical semiconductor device including an electrode including a layer structure which may be Zn, and a refractory metal layer as a first layer and AgZn as a second layer on the semiconductor layer of the optical semiconductor device.
Alternatively, an optical semiconductor device is characterized in that an electrode including an Ag / Zn / Ag or Zn layer is provided. Ti, Ph, Pd, etc. are preferably used as the high melting point metal layer, and the thickness of the high melting point metal layer is preferably 100 Å or less.

On the electrode having the above layer structure, if necessary,
A structure for flip-chip such as Pt / AuSn can be additionally adopted through the second refractory metal layer. In the second embodiment of the present invention, as a method of increasing the reflectance without deteriorating the contact resistance, the contact metal is thinned to reduce the unevenness of the interface and the alloy layer thickness so that the metal layer used on the contact metal has high reflection. A, which is a metal
A high melting point metal is added as an intermediate layer by using g, Al, Au or the like to reflect the light transmitted through the thin contact metal and prevent reaction between the highly reflective metal and the contact metal or semiconductor.

Specifically, an electrode including an AuZn or AuGe layer as a first layer, a refractory metal layer as a second layer, and an Ag, Au or Al layer as a third layer is provided on a semiconductor layer of an optical semiconductor device. It is configured as an optical semiconductor device characterized by the above. The thickness of the second layer and the first layer is preferably 50 Å or less.

[0008]

EXAMPLES Example 1 An example of making a PIN-PD using the first mode of the present invention is shown below. FIG. 1 is an epi-wafer made for PIN-PD, which is formed on the N-InP substrate 1 by MO-CVD method.
nP buffer layer 2, N-InGaAs active layer 3, N
-InP cap layer 4 is 1 μm, 1 μm, 1
It is a grown μm. After forming a 10 μm-diameter PIN junction on this epiwafer by selective diffusion 5 of Zn, a visor-based AZ-based resist was used to form a canopy hole. On top of that, Ti (30
Å), Ag (50 Å), Zn (70 Å), Ag (880
The metal film 7 of Å) is sequentially formed by EB vapor deposition and resistance heating.

At this time, the relationship between the Ti film thickness and the light absorption rate is shown in FIG. It can be seen that the reflectance decreases by 20% when the Ti film thickness is 100Å. The reflectance tends to decrease as the amount of Zn increases. FIG. 9 shows the relationship between the Zn concentration of the InP substrate and the contact resistance of the Ti / AgZn electrode.
Contact resistance is 10 ^-4 Ω when the substrate concentration is 10 ¹⁸ cm ^-3 or more
It has fallen below cm.

Next, as shown in FIG.
After forming the side electrode b and sintering at 430 ° C., Si ₃ N
₄ film is patterned with AZ resist and NH ₄ O
Selective etching removal is performed with H + HF (5%) solution.
Next, as shown in FIG. 3, an N electrode and a P are formed by using an AZ resist.
The peripheral portion of the electrode is covered and the groove 7 is formed by ion beam etching or HB _r + B _r + H ₂ O mixed liquid. After that, the N-side pattern 9 is formed from AuGe metal by the same lift-off process as described above and alloyed at 380 ° C.

Next, as shown in FIG. 4, a SiN film 10 is attached by plasma CVD, and holes are formed on the electrodes on the P side and the N side, respectively. Next, as shown in FIG. 5, Ti, Pt, and AuSn are sequentially formed by EB vapor deposition and resistance heating vapor deposition with a thickness of 500 Å, 3000 Å, and 4 μm, and a multilayer electrode 11 is formed by ion beam etching using the AZ resist as a mask. ..

Next, as shown in FIG. 6, after processing the substrate to a thickness of 80 μm, a dome having a diameter of 50 μm is formed so that the center of the light receiving portion and the apex of the AZ resist meet. After forming the monolithic lens 12 that focuses on the center of the light receiving part by ion beam etching, AR of Si ₃ N ₄ is formed.
(Antireflection) coat 13 is applied. Example 2 An example in which the first embodiment of the present invention is applied to a light emitting diode will be shown below.

FIG. 10 is a final structural diagram when applied to a light emitting diode with an InP microlens. The P electrode portion is lifted by an AZ resist on InGaAsP.
The electrode pattern was formed by the off method. Ti (30
Å) / [Ag (50Å) / Zn (70Å)] / Ag (8
After depositing 80 Å) and patterning it, heat treatment is performed at 450 ° C. for 3 minutes to deposit Ti / Pt metal. further,
A film for Au bonding and heat sink is formed by plating to a thickness of about 5 μm.

The other structures are as shown in the figure and are conventionally known structures. Example 3 An example in which the second embodiment of the present invention is applied to a back illuminated PIN-PD and produced. FIG. 11 shows N ⁺ -I on the InP substrate 31.
nP buffer layer 32, N ⁻ -InGaAs light absorption layer 3
3. The N-InP layer 34 is sequentially grown, the SiN film 35 is attached, the Zn diffusion window is opened, and the selective diffusion 36 is performed.

Next, as shown in FIG. 12, a resist hole is formed on the diffusion layer 36 with an AZ-based resist, and Au / Zn / A is formed.
After depositing the u film (50Å) 37 by resistance heating, the resist is removed to form a pattern. Next, as shown in FIG.
After heat treatment at 30 ° C., a Si ₃ N ₄ film 38 is attached, a resist pattern hole smaller than the diameter of the contact metal is formed on the diffusion layer 36, and SiN is selectively etched. Next, as shown in FIG. 13, after forming a pattern in which the electrodes are opened with Az resist, Ti / Ag / Ti / Pt is formed.
The / AuSn film 38 is formed by EB vapor deposition and resistance heating.

Next, as shown in FIG. 14, an electrode 40 is formed by Ar ion beam etching using the AZ resist as a mask. In this example, the N-side electrode was omitted and only the skeleton of the P-side electrode was described. FIG. 15 shows an overall view of the PIN-PD thus produced. FIG. 16 shows AuZnAu.
After alloying / InP at 430 ° C. for 3 minutes, an Au layer (thickness of 300 Å) was formed as a reflective layer, and the reflectance was obtained. The same result was obtained by using the Ag layer instead of the Au layer.

FIG. 17 shows Zn-doped 5 × 10 5¹⁸cm^-3I
Alloy layer when AuZnAu is alloyed on nP substrate
The relationship between thickness and contact resistivity is shown. This second form
In the following, the following effects can be obtained. Quantum efficiency of photo detector
Is represented by η = 1-exp (-αw), and α is 1 × 10^Four
cm ^-1In the case of, the light receiving element having a 1 μm absorption layer is η =
63%, but according to the present invention a highly efficient reflective electrode (eg
For example, when 48%) is used, it is improved to 81%. That
The contact resistance hardly changes at the time, and AuZn system is good.
While maintaining excellent characteristics, low contact resistance and high quantum efficiency
A surface incident type light receiving element can be realized.

[0018]

According to the first aspect of the present invention, an alloying reaction between a high-reflectance metal and a semiconductor is performed by using a high-reflectance metal on a compound semiconductor and interposing a thin refractory metal layer therebetween. Was prevented. As a result, it was possible to suppress a decrease in reflectance due to alloying while using a high reflectance metal. If ohmic contact is required, Zn is added to Ag.
An electrode having a high resistivity and a high reflectance can be realized by doping the substrate by mixing in the electrode.

According to the second aspect of the present invention, an alloy layer is thinly formed on the compound semiconductor in order to improve the reflectance without deteriorating the contact resistance, and a high reflectance metal is used on the alloy layer to increase the reflectance. The reflectance was realized, and the refractory metal layer was thinly interposed between them to prevent alloying of the high reflectance metal. As a result, low contact resistance and high reflectance are realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a principal part of a process of creating a PIN-PD according to a first embodiment.

FIG. 2 is a sectional view of a principal part of a process of forming a PIN-PD according to the first embodiment.

FIG. 3 is a sectional view of a principal part of a process of forming a PIN-PD according to the first embodiment.

FIG. 4 is a sectional view of a principal part of a process of forming a PIN-PD according to the first embodiment.

FIG. 5 is a sectional view of a principal part of a process of forming a PIN-PD according to the first embodiment.

FIG. 6 is a sectional view of a principal part of a process of forming a PIN-PD according to the first embodiment.

FIG. 7 is a cross-sectional view of the PIN-PD created in Example 1.

FIG. 8 is a relationship diagram between the thickness of a Ti film and the light absorption rate.

FIG. 9 is a diagram showing the relationship between the contact resistance of a Ti / AgZn electrode on an InP substrate and the substrate concentration.

FIG. 10 is a cross-sectional view of a light emitting diode of Example 2.

FIG. 11 is a sectional view of a principal part of a process for producing a PIN-PD according to a third embodiment.

FIG. 12 is a sectional view of a principal part of a process for forming a PIN-PD according to a third embodiment.

FIG. 13 is a sectional view of a principal part of a process for forming a PIN-PD according to a third embodiment.

FIG. 14 is a sectional view of a principal part of a process for forming a PIN-PD according to a third embodiment.

FIG. 15 is a sectional view of a PIN-PD according to a third embodiment.

FIG. 16 is a diagram showing the relationship between the light reflectance and the layer thickness of the AuZn alloy layer on the surface of the InP substrate.

FIG. 17: AnZ of InP substrate (5 × 10 ¹⁸ cm ⁻³ ) surface
It is a figure which shows the relationship between the layer thickness of an n alloy layer, and contact resistance.

[Explanation of symbols]

 1 ... N-InP substrate 2 ... N-InP buffer layer 3 ... N-InGaAs active layer 4 ... InP cap layer 5 ... Zn selective diffusion layer

Claims (7)

[Claims] 1. On a semiconductor layer of an optical semiconductor device, a refractory metal layer as a first layer, an Ag, Al layer as a second layer, a Zn, Ge or Sn layer as a third layer, and a fourth layer is Ag or Al. A second layer Ag or Al, a third layer Zn and a fourth layer
AgZn or AlZn by alloying with Ag or Al of the layer
An optical semiconductor device comprising an electrode having a layer structure which may be provided. 2. The optical semiconductor device according to claim 1, wherein the refractory metal layer has a thickness of 100 Å or less. 3. The optical semiconductor device according to claim 1, further comprising a second refractory metal layer on the fourth layer. 4. A refractory metal layer as a first layer and AgZn or Ag / Z as a second layer on a semiconductor layer of an optical semiconductor device.
An optical semiconductor device comprising an n / Ag or Zn layer and an electrode including a second refractory metal layer as a third layer. 5. An electrode including an AuZn or AuGe layer as a first layer, a refractory metal layer as a second layer, and an Ag, Au or Al layer as a third layer is provided on a semiconductor layer of an optical semiconductor device. A characteristic optical semiconductor device. 6. The optical semiconductor device according to claim 5, wherein the second layer has a thickness of 100 Å or less. 7. The optical semiconductor device according to claim 5, wherein the first layer has a thickness of 50 Å or less.