KR900019234A - 반도체기억장치 - Google Patents

반도체기억장치 Download PDF

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Publication number
KR900019234A
KR900019234A KR1019900006639A KR900006639A KR900019234A KR 900019234 A KR900019234 A KR 900019234A KR 1019900006639 A KR1019900006639 A KR 1019900006639A KR 900006639 A KR900006639 A KR 900006639A KR 900019234 A KR900019234 A KR 900019234A
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KR
South Korea
Prior art keywords
insulating film
semiconductor substrate
memory device
semiconductor memory
charge storage
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Application number
KR1019900006639A
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English (en)
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KR940001424B1 (ko
Inventor
줌페이 구마가이
시즈오 사와다
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR900019234A publication Critical patent/KR900019234A/ko
Application granted granted Critical
Publication of KR940001424B1 publication Critical patent/KR940001424B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체기억장치에 형성되는 다이내믹형 메모리세의 1 실시예를 나타낸 단면도, 제2도(a)∼(d)는 제1도에 도시된 메모리셀의 제조방법의 1 실시예에 따른 각 공정에서의 기판을 나타낸 단면도, 제3도는 제1도에 도시된 메모리셀의 등가회로도.

Claims (3)

1개의 전하전송용 트랜지스터(TR)와 1개의 전하축적용 캐패시터(C1, C2)로 이루어진 다이내믹형 메모리셀 어레이를 갖춘 반도체 기억장치에 있어서, 상기 트랜지스터(TR)는 제1도전형 반도체기판(1)상에 형성된 제2도전형 웰영역(3)의 표면에 형성되고 ; 상기 캐패시터(C1, C2)는 상기 웰영역(3)의 표면으로부터 상기 반도체기판(1)에 도달하도록 형성된 미세구멍(8)의 내면에 형성되어진 제1절연막(9)과, 상기 미세구멍(8) 내에서 상기 제1 절연막(9)상에 매립-형성된 전하축적전극(11), 상기 미세구멍(8)내에서 상기 전하축적전극(11)상에 형성된 제2절연막(12), 일부가 상기 미세구멍(8)내에서 상기 제2절연막(12)상에 매립·형성된 캐패시터 플레이트 전극(13)으로 이루어지며 ; 상기 제1절연막(9)의 두께가 제2절연막(12)의 두께보다 두꺼운 것을 특징으로 하는 반도체 기억장치.
제1항에 있어서, 상기 제1도전형 반도체기판(1)은 1×1018∼1×1021㎤의 농도로 불순물이 도우프된 제1도 전형 반도체기판상에 에피택셜 성장층(2)이 형성되어 이루어진 것을 특징으로 하는 반도체기억장치.
제1항에 있어서, 상기 제1도전형 반도체기판(1)은 1×1018∼1×1018㎤의 농도로 불순물이 도우프된 제1도 전형 반도체기판만으로 이루어진 것을 특징으로 하는 반도체기억장치.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900006639A 1989-05-15 1990-05-10 반도체 기억장치 KR940001424B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1121203A JPH0770617B2 (ja) 1989-05-15 1989-05-15 半導体記憶装置
JP1-121203 1989-05-15

Publications (2)

Publication Number Publication Date
KR900019234A true KR900019234A (ko) 1990-12-24
KR940001424B1 KR940001424B1 (ko) 1994-02-23

Family

ID=14805419

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900006639A KR940001424B1 (ko) 1989-05-15 1990-05-10 반도체 기억장치

Country Status (5)

Country Link
US (1) US5041887A (ko)
EP (1) EP0398249B1 (ko)
JP (1) JPH0770617B2 (ko)
KR (1) KR940001424B1 (ko)
DE (1) DE69027953T2 (ko)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920004368B1 (ko) * 1989-09-04 1992-06-04 재단법인 한국전자통신연구소 분리병합형 홈의 구조를 갖는 d램셀과 그 제조방법
JPH04328861A (ja) * 1991-04-26 1992-11-17 Texas Instr Japan Ltd 半導体集積回路装置及びその製造方法
KR940006681B1 (ko) * 1991-10-12 1994-07-25 금성일렉트론 주식회사 스택트렌치 셀 및 그 제조방법
JP2924395B2 (ja) * 1992-01-09 1999-07-26 日本電気株式会社 半導体装置の製造方法
JP2827728B2 (ja) * 1992-08-03 1998-11-25 日本電気株式会社 半導体記憶装置およびその製造方法
US5466636A (en) * 1992-09-17 1995-11-14 International Business Machines Corporation Method of forming borderless contacts using a removable mandrel
US5283453A (en) * 1992-10-02 1994-02-01 International Business Machines Corporation Trench sidewall structure
US5363327A (en) * 1993-01-19 1994-11-08 International Business Machines Corporation Buried-sidewall-strap two transistor one capacitor trench cell
US5422294A (en) * 1993-05-03 1995-06-06 Noble, Jr.; Wendell P. Method of making a trench capacitor field shield with sidewall contact
US5492853A (en) * 1994-03-11 1996-02-20 Micron Semiconductor, Inc. Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device
US5448090A (en) * 1994-08-03 1995-09-05 International Business Machines Corporation Structure for reducing parasitic leakage in a memory array with merged isolation and node trench construction
US6090661A (en) 1998-03-19 2000-07-18 Lsi Logic Corporation Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls
US6369418B1 (en) 1998-03-19 2002-04-09 Lsi Logic Corporation Formation of a novel DRAM cell
US6177699B1 (en) 1998-03-19 2001-01-23 Lsi Logic Corporation DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation
US6271557B1 (en) * 1999-10-05 2001-08-07 Infineon Technologies Ag Center node for deep trench capacitors
DE10053966A1 (de) * 2000-10-31 2002-05-23 Infineon Technologies Ag DRAM-Speicherzelle
DE10133874A1 (de) * 2001-07-12 2003-02-20 Infineon Technologies Ag Speicherzelle mit einem zweiten Transistor zum Halten eines Ladungswertes
US8232624B2 (en) 2009-09-14 2012-07-31 International Business Machines Corporation Semiconductor structure having varactor with parallel DC path adjacent thereto
US10650978B2 (en) 2017-12-15 2020-05-12 Micron Technology, Inc. Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb
US11031404B2 (en) * 2018-11-26 2021-06-08 Etron Technology, Inc. Dynamic memory structure with a shared counter electrode

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184053A (ja) * 1984-10-01 1986-04-28 Hitachi Ltd 半導体装置
US4688063A (en) * 1984-06-29 1987-08-18 International Business Machines Corporation Dynamic ram cell with MOS trench capacitor in CMOS
JPS6187358A (ja) * 1984-10-05 1986-05-02 Nec Corp 半導体記憶装置およびその製造方法
JPS61258468A (ja) * 1985-05-13 1986-11-15 Hitachi Ltd 半導体記憶装置およびその製造方法
JPH0666439B2 (ja) * 1985-11-12 1994-08-24 日本電気株式会社 半導体記憶装置
US4785337A (en) * 1986-10-17 1988-11-15 International Business Machines Corporation Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes
JPH0810755B2 (ja) * 1986-10-22 1996-01-31 沖電気工業株式会社 半導体メモリの製造方法
JPS63207171A (ja) * 1987-02-24 1988-08-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ装置及びその製造方法
JPS63209158A (ja) * 1987-02-25 1988-08-30 Mitsubishi Electric Corp １トランジスタ型ダイナミツクメモリセル
US4794434A (en) * 1987-07-06 1988-12-27 Motorola, Inc. Trench cell for a dram

Also Published As

Publication number Publication date
JPH02301164A (ja) 1990-12-13
EP0398249B1 (en) 1996-07-31
DE69027953D1 (de) 1996-09-05
EP0398249A3 (en) 1991-06-26
DE69027953T2 (de) 1997-01-02
JPH0770617B2 (ja) 1995-07-31
US5041887A (en) 1991-08-20
KR940001424B1 (ko) 1994-02-23
EP0398249A2 (en) 1990-11-22

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