KR940022840A - 반도체 장치의 메모리셀 제조방법 및 구조 - Google Patents

반도체 장치의 메모리셀 제조방법 및 구조 Download PDF

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KR940022840A
KR940022840A KR1019930004375A KR930004375A KR940022840A KR 940022840 A KR940022840 A KR 940022840A KR 1019930004375 A KR1019930004375 A KR 1019930004375A KR 930004375 A KR930004375 A KR 930004375A KR 940022840 A KR940022840 A KR 940022840A
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South Korea
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forming
semiconductor
memory cell
film
layer
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KR1019930004375A
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KR0135067B1 (ko
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최종무
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문정환
금성일렉트론 주식회사
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Priority to KR1019930004375A priority Critical patent/KR0135067B1/ko
Priority to DE4407532A priority patent/DE4407532C2/de
Priority to US08/207,769 priority patent/US5418177A/en
Priority to JP6048637A priority patent/JP2686228B2/ja
Publication of KR940022840A publication Critical patent/KR940022840A/ko
Priority to US08/730,256 priority patent/US5650957A/en
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Publication of KR0135067B1 publication Critical patent/KR0135067B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 장치의 메모리셀 제조방법 및 구조에 관한 것으로서, 특히 캐패시턴스의 용량 증가를 위해 캐패시터를 트랜지스터 하부에 위치되도록하여 고집적 반도체 제조에 적당하도록 한 반도체 장치의 메모리셀 제조방법 및 그 구조에 관한 것이다.
이를 위하여 반도체 장치의 메모리셀 구조에 있어서, 반도체 장치의 메모리셀 제조 구조에 있어서, 반도체 기판에 평판상으로 형성된 저장전극, 유전체막, 플레이트 전극으로 된 매입 캐패시터와, 상기 캐패시터 상부에 형성되고 상기 캐패시터의 저장전극과 하나의 소오스 드레인 영역이 전기적으로 접속된 트랜지스터로 되어 대용량의 캐패시턴스를 구현하고, 트랜지스터가 박막으로 제조됨에 따라 게이트를 절연막으로 감싸도록하여 소스/드레인간의 누설전류를 현저히 감소시킬 수 있다.

Description

반도체 장치의 메로리셀 제조방법 및 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 반도체 장치의 메로리셀 제조 공정도 및 구조도.

Claims (5)

  1. 반도체 장치의 메모리셀 구조에 있어서, 반도체 장치의 메모리셀 제조 구조에 있어서, 반도체 기판위에 제1유전체막을 형성하는 단계; 상기 제1유전체 막위에 제1반도체층을 형성하고, 소정영역을 식각하여 저장전극을 형성하는 단계; 상기 저장전극 위에 제2유전체막을 형성하고, 전면에 제2반도체층으로 플레이트 전극을 형성하는 단계; 상기 플레이트 전극위에 절연막을 형성하고, 이방성식각으로 접촉창 측면에 제3유전체막을 형성하는 단계; 상기 접촉창에 반도체층으로 연결층을 형성하고 전면에 제3반도체층을 형성하는 단계; 상기 제3반도체층위에 활성영역과 격리영역을 정의하고, 격리영역의 제3반도체층을 선택적으로 식각하고 절연막을 채워 소자 격리막을 형성하는 단계를 포함하는 반도체 장치의 메모리셀 제조방법.
  2. 제1항에 있어서, 상기 제1 내지 제3반도체층은, 도핑된 폴리실리콘을 사용한 것을 특징으로 하는 반도체 장치의 메모리셀 제조방법.
  3. 제1항에 있어서, 상기 절연막 및 소자격리막은 CVD 산화막으로 형성한 것을 특징으로 하는 반도체 장치의 메모리셀 제조방법.
  4. 반도체 장치의 메모리셀 구조에 있어서, 반도체 기판에 저장전극, 유전체막, 플레이트 전극이 평판상으로 형성된 매립 캐패시터와, 상기 캐패시터 상부에 형성되고 상기 캐패시커의 저장전극과 하나의 소오스 드레인 영역이 전기적으로 접속된 트랜지스터로 이루어진 반도체 장치의 메모리셀 구조.
  5. 제4항에 있어서, 상기 캐패시터는, 반도체 기판위에 평면상으로 형성된 제1유전체막, 상기 제1유전체 막위에 제1반도체층으로 된 소정면적으로 구분된 저장전극, 상기 저장전극 위에 형성된 제2유전체막, 상기 제2유전체막위에 형성된 플레이트 전극, 상기 플레이트 전극위에 형성된 절연막, 상기 절연막과 플레이트 전극을 관통하고, 플레이트 전극과는 절연되며, 저장전극과 전기적으로 접속되는 연결기둥, 상기 연결기둥과 접속되고 필드절연막으로 결리되며 게이트와 소오스/드레인 영역이 형성된 제3반도체층으로 이루어지는 반도체 장치의 메모리셀 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930004375A 1993-03-22 1993-03-22 반도체 장치의 메모리셀 제조방법 및 구조 KR0135067B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019930004375A KR0135067B1 (ko) 1993-03-22 1993-03-22 반도체 장치의 메모리셀 제조방법 및 구조
DE4407532A DE4407532C2 (de) 1993-03-22 1994-03-07 DRAM-Speicherzelle und Verfahren zur Herstellung derselben
US08/207,769 US5418177A (en) 1993-03-22 1994-03-07 Process for formation of memory cell where capacitor is disposed below a transistor
JP6048637A JP2686228B2 (ja) 1993-03-22 1994-03-18 半導体メモリセル及びその製造方法
US08/730,256 US5650957A (en) 1993-03-22 1996-10-15 Semiconductor memory cell and process for formation thereof

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Application Number Priority Date Filing Date Title
KR1019930004375A KR0135067B1 (ko) 1993-03-22 1993-03-22 반도체 장치의 메모리셀 제조방법 및 구조

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KR940022840A true KR940022840A (ko) 1994-10-21
KR0135067B1 KR0135067B1 (ko) 1998-04-20

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US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US6242772B1 (en) 1994-12-12 2001-06-05 Altera Corporation Multi-sided capacitor in an integrated circuit
US5585285A (en) * 1995-12-06 1996-12-17 Micron Technology, Inc. Method of forming dynamic random access memory circuitry using SOI and isolation trenches
US5731217A (en) * 1996-10-08 1998-03-24 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a filled upper transistor substrate and interconnection thereto
US5872029A (en) * 1996-11-07 1999-02-16 Advanced Micro Devices, Inc. Method for forming an ultra high density inverter using a stacked transistor arrangement
US5926700A (en) 1997-05-02 1999-07-20 Advanced Micro Devices, Inc. Semiconductor fabrication having multi-level transistors and high density interconnect therebetween
US5888872A (en) 1997-06-20 1999-03-30 Advanced Micro Devices, Inc. Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall
US5818069A (en) 1997-06-20 1998-10-06 Advanced Micro Devices, Inc. Ultra high density series-connected transistors formed on separate elevational levels
US6242298B1 (en) * 1997-08-29 2001-06-05 Kabushiki Kaisha Toshiba Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same
US5843820A (en) 1997-09-29 1998-12-01 Vanguard International Semiconductor Corporation Method of fabricating a new dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor
US5976945A (en) * 1997-11-20 1999-11-02 Vanguard International Semiconductor Corporation Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
CN114695268B (zh) * 2020-12-30 2024-06-21 长鑫存储技术有限公司 存储器及其制作方法

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KR920010461B1 (ko) * 1983-09-28 1992-11-28 가부시끼가이샤 히다찌세이사꾸쇼 반도체 메모리와 그 제조 방법
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JPS6224379A (ja) * 1985-07-24 1987-02-02 Matsushita Electric Ind Co Ltd 手動副走査形読取装置
JPS62133755A (ja) * 1985-12-06 1987-06-16 Sony Corp 半導体装置
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Also Published As

Publication number Publication date
JP2686228B2 (ja) 1997-12-08
DE4407532C2 (de) 1998-07-02
JPH06326271A (ja) 1994-11-25
US5650957A (en) 1997-07-22
US5418177A (en) 1995-05-23
DE4407532A1 (de) 1994-09-29
KR0135067B1 (ko) 1998-04-20

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