WO1991018418A1

WO1991018418A1 - Semiconductor memory device and method of manufacturing the same

Info

Publication number: WO1991018418A1
Application number: PCT/JP1991/000655
Authority: WO
Inventors: Akio Kita
Original assignee: Oki Electric Industry Co., Ltd.
Priority date: 1990-05-23
Filing date: 1991-05-17
Publication date: 1991-11-28

Abstract

In a semiconductor memory device having cells of one-transistor one-capacitor type, a switching transistor (21) is sandwiched between a capacitor (13) and a bit line (29).

Description

Technical Field Semiconductor memory device and method of manufacturing the same

The present invention relates to a dynamic memory device (hereinafter, referred to as DRAM) having a MIS (Metal Insulator Semiconductor) structure. Background art

The DRAM is a high-density implementation of one transistor and one canopy-type memory cell. The area of this memory cell becomes smaller with higher integration. On the other hand, even when unnecessary charges such as leak current and alpha particles flow into the capacitor, the memory cell needs to perform stable storage operation. Therefore, the three-dimensional structure is used

One of the three-dimensional structures is stack capacity. The structure of a conventional semiconductor memory device using this stack capacity will be described with reference to a cross-sectional view shown in FIG.

The conventional semiconductor memory device 40 shown in the figure has a silicon substrate 41, a field oxide film 42 formed on the surface of the silicon substrate 41, and a field oxide film 42. The switching transistor 43 formed on the silicon substrate 41 adjacent to the gate oxide film 42 and the surface of the insulating film 45 covering the switching transistor 43 and the field oxidation. It is composed of a stack capacity 46 formed on the surface of the film 42. The switching transistor 43 includes a gate oxide film 47 formed on the surface of the P-type silicon substrate 41 and a gate electrode 48 formed on the upper surface of the gate oxide film 47. And a source / drain diffusion layer 49, 5 した connected to the gate oxide film 47 in the P-type silicon substrate 41 on both sides of the gate oxide film 48.

The storage capacitor 46 includes a storage node electrode 51 formed on each surface of the insulating film 45 and the field oxide film 42, and a storage node. C composed of a dielectric thin film 52 covering the surface of the pad electrode 51, a dielectric thin film, and a plate electrode 53 formed on the surface of the dielectric thin film 52. On the entire surface on the 46 side, an interlayer insulating film 54 is formed. In this interlayer insulating film 54, a bit contact hole 55 reaching the source drain diffusion layer 50 is provided. Further, on the surface of the interlayer insulating film 54, a bit line 56 connected to the source drain diffusion layer 50 via a bit connector hole 55 is provided. A passivation film 57 is formed on the entire surface of the bit line 56.

However, in the conventional semiconductor memory device having the above configuration, a capacity cannot be formed in a region where a bit contact hole is formed. For this reason, in a 16-megabit DRAM or a 64-megabit DRAM with a small memory cell area, the capacitance cannot be sufficiently secured, and the reliability is reduced.

In addition, if alpha particles enter from the silicon substrate side, In this case, the so-called soft error occurs in which the carriers generated by the alpha particles flow into the capacity through the source-drain diffusion layer and destroy the accumulated information.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a highly reliable semiconductor memory device in which the capacitance of a capacitor is increased to reduce soft errors and a method of manufacturing the same. aimed to. Disclosure of the invention

According to a first embodiment of the present invention, there is provided a capacitor in which a semiconductor memory device is formed on a rigid substrate via a first insulating film to achieve the above object,

The capacitor is formed on the capacitor via a second insulating film, and is connected to the capacitor via a conductive material formed in a first contact hole provided in the second insulating film. A transistor and

A bit formed on the transistor via a third insulating film, and connected to the transistor via a second connector hole provided in the third insulating film;

It has.

Further, a second embodiment of the present invention is directed to a semiconductor memory device having a bit line formed on a rigid substrate via a first insulating film to achieve the above object.

The first contact hole is formed on the bit line via a second insulating film, and is provided in the second insulating film. A transistor connected to the bit line via a conductive material formed at

A stack transistor formed on the transistor via a third insulating film, and connected to the transistor via a second contact hole provided in the third insulating film; Evening

It has.

Further, the present invention provides a process for forming a first insulating film on a substrate and forming a capacitor on the surface of the first insulating film in order to manufacture a semiconductor memory device having the configuration of the first embodiment. Forming a second insulating film on the entire surface on the side, further forming a contact portion, and planarizing the entire surface; attaching a single crystal semiconductor to the surface of the second insulating film; Forming a conductor in an island-shaped single crystal semiconductor pattern; forming a gate oxide film, a gate electrode and each source drain diffusion layer on the single crystal semiconductor pattern; and forming an entire surface on the gate electrode side. Forming a third insulating film, providing a bit contact hole, and arranging the bit line.

Further, according to the present invention, in order to manufacture the semiconductor memory device having the configuration of the second embodiment described above, a first insulating film is formed on a substrate, and a bit line is provided on the surface of the first insulating film. A step of forming a second insulating film on the entire surface on the bit line side, further forming a contact portion and flattening the entire surface, and attaching a single crystal semiconductor to the surface of the second insulating film. Forming an island-shaped single-crystal semiconductor pattern, and expanding a gate oxide film, a gate electrode, and each source drain on the single-crystal semiconductor pattern. The method includes a step of forming a diffused layer and a step of forming a third insulating film on the entire surface on the gate electrode side, providing a contact hole, and forming a stack capacitor.

Therefore, the semiconductor memory device of the first embodiment described above has a second source drain diffusion layer and a bit line connected to each other through a bit contact hole provided in the third insulating film. 1 Only the capacity is provided on the surface of the insulating film.

Therefore, since the capacity is formed in an area having a sufficient capacitance, it is possible to prevent the destruction of stored information caused by unnecessary charges flowing into the capacitor. .

In addition, since each insulating film blocks the alpha particles that are going to enter the capacitor, the occurrence of soft errors is reduced.

In the semiconductor memory device of the second embodiment, the bit line and the second source / drain diffusion layer are connected via a contact portion provided in the second insulating film. On the surface of the third insulating film, only a stack capacitor is provided.

Therefore, since the stack capacitor is formed in an area having a sufficient capacitance, it is possible to prevent the accumulated information from spilling due to unnecessary charges flowing into the stack capacity.

In addition, the occurrence of soft errors is reduced by blocking each of the insulating films from the alpha particles that are going to be incident on the stack capacity. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a layout pattern diagram of the first embodiment of the present invention.

FIG. 3 is a process chart of the manufacturing method according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a second embodiment of the present invention.

FIG. 5 is a layout pattern diagram of a second embodiment of the present invention. ...

FIG. 6 is a diagram of a manufacturing method according to a second embodiment of the present invention: .

FIG. 7 is a sectional view of a conventional device. BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment>

A first embodiment of the present invention will be described with reference to a sectional view shown in FIG. Fig. 1 shows a 2-bit semiconductor memory device.

The substrate 11 shown in the figure is formed of silicon. The substrate 11 may have any rigidity and may have any electrical properties.

A first insulating film 12 is formed on a surface of the substrate 11. The first insulating film 1 2 is formed in oxide film (S i 0 _2), wherein the first insulating film 1 a second surface, the capacitor 1 3, 1 3 are formed.

The capacitor 13 is provided on the surface of the first insulating film 12. It is composed of a plate electrode 14 formed, a dielectric thin film 15 formed on the surface of the plate electrode 14, and a storage node electrode 16 formed on the surface of the dielectric thin film 15. It is a stack capacitor.

The plate electrode 14 is formed of polysilicon having a high concentration of phosphorus, and is used in common with the adjacent capacitor 13. The dielectric thin film 15 is formed of silicon nitride. Further, the storage node electrode 16 is formed of polysilicon. Further, the storage node electrode 16 is formed with a maximum size that does not contact the adjacent storage node electrodes.

A second insulating film 17 is formed of an oxide film on the entire surface on the capacity 13 side.

The second insulating film 17 is provided with a contact hole 18 that reaches each of the storage node electrodes 16. Each contact hole 18 is filled with polysilicon to form a contact portion 19. The surface of each contact portion 19 and the surface of the second insulating film 17 are arranged so as to form one plane.

A single crystal semiconductor pattern 20 is formed on the surface of the second insulating film 17. Further, the lower surfaces on both sides of the single crystal semiconductor substrate 20 are connected to the contact portions 19, 19, respectively.

Switching transistors 21 and 21 are formed in this single crystal semiconductor pattern 20.

Each switching transistor 21 is connected to the single crystal semiconductor. A gate oxide film 22 formed on the upper surface of the body pattern 20; a gate electrode 23 formed on the upper surface of the gate oxide film 22; and a single crystal on one side of the gate oxide film 22. A first source drain diffusion layer 24 formed on the semiconductor pattern 20 and a second source drain diffusion layer formed on the single crystal semiconductor pattern 20 on the other side of the gate oxide film 22 25. The gate electrode 23 is formed of polysilicon. Each of the first source drain diffusion layers 24 is connected to the connection part 19 and one side of the gate oxide film 22. -, ·

The second source / drain diffusion layer 24 is shared with the adjacent switching transistor 21 and is connected to the other side of each of the gate oxide films 22 and 22.

Further, a gate electrode wiring 26 formed of polysilicon is provided on the surface of the second insulating film 1 except for the region where the single crystal semiconductor pattern 20 is formed. .

A third insulating film 27 made of an oxide film is formed on the entire surface of the switching transistor 21 side.

The third insulating film 27 is provided with a bit connection hole 28 reaching the second source drain diffusion layer 25. On the surface of the third insulating film 27, a bit line 29 connected to the second source drain diffusion layer 25 through the bit contact hole 28 is provided. Further, a fourth insulating film 30 is formed on the entire surface on the bit line 29 side.

This fourth insulating film 30 has 16 cells or 32 cells Further, a lead contact hole (not shown) reaching the gate electrode 23 is provided.

On the surface of the third insulating film 27, a lead wire 31 connected to the gate electrode 23 through the lead contact hole is provided. This word line 31 is formed of a metal such as aluminum or an aluminum alloy. Therefore, the wiring resistance of the gate electrode wiring 26 is reduced.

Further, a passivation film 32 is formed on the entire surface of the word line 31 side.

In the semiconductor memory device having the above-described configuration, as shown in FIG. 2 ', each storage node electrode 16 forming a plurality of capacitors 13 is disposed adjacent to each other, and further, a plurality of switching transformers are provided. The single crystal semiconductor patterns 20 forming the transistors 21 are arranged adjacent to each other.

The gate electrode 23 (a perspective portion in the figure) is connected to the other gate electrode by a gate electrode wiring 26 that is substantially orthogonal to the longitudinal direction of the storage node electrode 16. (Not shown).

Further, the bit line 29 is disposed in the longitudinal direction on the single-crystal semiconductor padder 20, and the second source drain diffusion layer 25 of each switching transistor 21 is passed through each bit contact hole 28. Connected to.

On the other hand, the word line 31 is arranged on the gate electrode 23 in parallel with the gate electrode wiring 26 connected to the gate electrode 23.

Next, the basic operation of the above-described semiconductor memory device will be described. O

In a write or read operation, the voltage of the word line 31 is set to a high level, the switching transistor 21 is conducted, and the capacitance 13 and the bit line 29 are electrically connected. Done. When the voltage of the word line 31 is at a low level, the switching transistor 21 is turned off, the charge is held in the capacitor 13, and the information is stored.

Next, a method of manufacturing the above-described semiconductor memory device will be described with reference to FIGS.

As shown in FIG. 3A, a first insulating film 12 of an oxide film having a thickness of about 500 nm is formed on the surface of a silicon substrate 11 by a thermal oxidation method. Next, a polysilicon film having a thickness of about 400 nm is deposited by the reduced ECCV method. Subsequently, a high concentration of phosphorus is introduced into the polysilicon film by ion implantation to form a plate electrode 14. Next, a silicon nitride film is deposited to a thickness of about 10 nm by a reduced pressure CVD method, and a polysilicon film is further deposited by a reduced pressure CVD method. It is patterned by photolithography and etching techniques to form a storage node electrode 16 made of polysilicon and a dielectric thin film 1 made of silicon nitride. Form 5

Next, as shown in FIG. 3A, an oxide film is deposited to a thickness equal to or greater than the height of the storage node electrode 16 (approximately 2000 nra) by a CVD method to form a second insulating film 17. Next, using photolithography technology and etching technology, A contact hole 18 is formed. In addition, polysilicon is deposited by the CD method to a thickness such that the contact hole 18 is filled. Next, a contact portion 19 is formed by an etch-back technique while leaving the polysilicon only inside the contact hole 18. Then, the thickness of the second insulating film 17 is reduced to 500 nm to 10 nm by precision polishing, for example, polishing, and the surface of the second insulating film 17 and the connection portion 19 are formed. Is formed on a smooth surface in a state where the two surfaces are arranged on one plane.

Next, as shown in Fig. 3 (3), an oxide film is

Form 3 3. Then, a single crystal semiconductor P-type (100) silicon single crystal 35 whose surface is precisely polished and flattened is brought into contact with the surface of the second insulating film 17 and the surface of the contact portion 19. Then, a heat treatment at 110 ° C. is performed. Then, it is adhered by Van der Ruska.

Next, the P-type (100) silicon single crystal 35 is precisely polished until the film thickness becomes 500 nm to 100 nm. Thereafter, an island-shaped single-crystal semiconductor pattern 20 shown in FIG. 3 is formed by photolithography technology and etching technology.

Next, as shown in FIG. 3A, an oxide film having a thickness of 15 nm and serving as a gate oxide film 22 is formed on the surface of the single crystal semiconductor pattern 20 by a thermal oxidation method. Further, boron ions are implanted into the single crystal semiconductor substrate 20 by an ion implantation method. Subsequently, a polysilicon for forming the gate electrode 23 and the gate electrode wiring 23 is formed by a CVD method. Deposits at a thickness of approximately 300 nra. In addition, a high concentration of phosphorus ions is introduced into the polysilicon by ion implantation. Then, the gate electrode 23, the gate oxide film 22 and the gate electrode wiring 26 are formed by the photolithography technique and the etching technique. After that, arsenic is introduced at a high concentration into the single crystal semiconductor layer 20 by using the gate electrode 23 as a mask by ion implantation to form an N-type diffusion layer. This N-type diffusion layer forms the first source drain diffusion layer.

24 and a second source drain diffusion layer 25 are formed.

Next, as shown in FIG. 3A, an oxide film is deposited on the entire surface by a CVD method to form a third insulating film 27. Subsequently, a bit connection hole 28 is formed by photolithography technology and etching technology. Subsequently, tungsten is deposited on the entire surface, and thereafter, a bit line 29 is formed by patterning using photolithography technology and etching technology. In addition, the fourth insulating film

Boron phosphorus silicate glass (BPSG) which becomes 30 is formed. Subsequently, a word contact hole (not shown) is formed by the photolithography technique and the etching technique. Next, aluminum or an aluminum alloy is deposited by a sputtering method. Then, a word line 31 is formed by a photolithography technique and an etching technique. Further, a passivation film 32 is formed on the entire surface, and the wafer process is completed.

Second embodiment>

A second embodiment of the present invention will be described with reference to the sectional view of FIG. explain. Figure 4 shows a 2-bit semiconductor memory device. The same components as those in the first embodiment are denoted by the same reference numerals. The substrate 11 shown in the figure is made of, for example, silicon. The substrate 11 may have any rigidity and may have any electrical properties.

A first insulating film 12 is formed on a surface of the substrate 11. This first insulating film 1 2 oxide film (S i 0 ₂₎ _c of the first insulating film I 2 of surface to be formed, the bit Bokumaku 1 3 is arranged. The bit line 13 is formed of polysilicon into which a Ν-type impurity is introduced at a high concentration.

A second insulating film 14 made of an oxide film is formed on the entire surface of the bit line 13 side.

The second insulating film 14 is provided with a contact hole 15 reaching the bit line 13. This contact hole 15 is filled with polysilicon to form a contact portion.

16 is formed. The surface of the contact portion 16 and the surface of the second insulating film 4 are arranged so as to form one plane.

On the surface of the second insulating film 14, an island-shaped single crystal semiconductor pattern 17 is formed. Further, the central lower surface of the single crystal semiconductor panel 17 is connected to the contact section 16.

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In this single crystal semiconductor pattern 17, a switching transistor 18 is formed.

Each switching transistor 18 includes a gate oxide film 19 formed on the upper surface of the single crystal semiconductor pattern 17, A gate electrode 20 formed on the upper surface of the gate oxide film 19; a first source / drain diffusion layer 21 formed on the single crystal semiconductor pattern 1 on one side of the gate oxide film 20; The second source / drain diffusion layer 22 is formed in the single crystal semiconductor pattern 17 on the other side of the oxide film 19. The gate electrode 20 is formed of polysilicon. Each of the first source drain diffusion layers 21 is connected via a contact hole 25 to a storage capacitor electrode 27 of a stack capacity.

On the other hand, the second source / drain diffusion layer 22 is shared with the adjacent switching transistor 18 and is connected to the connection section 16.

Further, a gate electrode wiring 23 made of polysilicon is provided on the surface of the second insulating film 14 excluding the region where the single crystal semiconductor pattern is formed.

A third insulating film 24 made of an oxide film is formed on the entire surface of the switching transistor 18.

The third insulating film 24 is provided with a contact hole 25 that reaches each of the first source drain diffusion layers 21. The surface of the third insulating film 24 is A stack capacity 26 connected to the first source drain diffusion layer 21 through a contact hole 25 is provided. The stack capacitor 26 includes an island-shaped storage node electrode 27, a dielectric thin film 28, and a plate electrode 29.

The storage node electrode 27 is made of polysilicon. And formed on the side wall of one contact hole 25, the surface of the first source drain diffusion layer 21 and the surface of the third insulating film 24 in the contact hole 25. The dielectric thin film 28 is made of silicon nitride, and is formed on the entire surface of the storage node electrode 27. This dielectric thin film 28 may be formed only on the storage node electrode 27. Further, the plate electrode 29 is formed of a high-concentration phosphorus-introduced polysilicon. It is shared with the adjacent stack capacity 26. A fourth insulating film 30 is formed on the surface of the plate electrode 29.

The fourth insulating film 30 is provided with a word contact hole (not shown) that reaches the gate electrode 20 every 16 cells or 32 cells.

On the surface of the fourth insulating film 30, a lead wire 31 connected to the gate electrode 20 through the word contact hole is provided. The word line 31 is formed of a metal such as aluminum or an aluminum alloy. Therefore, the wiring resistance of the gate electrode wiring 23 is reduced.

Further, a passivation film 32 is formed on the entire surface on the word line 31 side.

In the semiconductor memory device having the above-described configuration, as shown in FIG. 5, each storage node electrode 27 forming a plurality of stack capacities 26 is disposed adjacent to each other. Each forming a plurality of switching transistors 18 _C-crystal semiconductor pattern 1 7 are adjacently disposed Further, the single crystal semiconductor patterns 1 7 is disposed in the longitudinal direction on the bit line 1 3, each Sui through each contactor isolation portion 1 6 It is connected to the second source drain diffusion layer 22 of the switching transistor 18.

In addition, the gate electrode 20 (shaded area in the figure) is

—Connected to another gate electrode (not shown) by a gate electrode wiring 23 substantially orthogonal to the longitudinal direction of the genode electrode 27.

Further, the gate line 31 is provided on the gate electrode 20 in parallel with the gate electrode wiring 23 connected to the gate electrode 20.

Next, the basic operation of the above-described semiconductor memory device will be described.

In a write or read operation, the voltage of the word line 31 is set to a high level, the switching transistor 18 is conducted, and the stack capacity 26 and the bit line 13 are electrically connected. It is done. When the voltage of the word line 31 is at a low level, the switching transistor 18 is turned off, the charge is held in the stack capacitor 26, and information is stored.

As shown in FIG. 6, an oxide film serving as the first insulating film 12 is formed on the surface of the silicon substrate 11 by a thermal oxidation method. Next, the film thickness is reduced to approximately A polysilicon film 33 of 400 nm is deposited. Subsequently, arsenic is introduced into the polysilicon film 33 at a high concentration using an ion implantation method.

Next, as shown in FIG. 6, the polysilicon film 33 is processed into a bit line 13 by using a photolithography technique and an etching technique. After that, the second insulating film 14 is formed by depositing an oxide film to a thickness equal to or more than the height of the bit line 13 (for example, 2000 nm) by using the CVD method. Next, contact holes 15 are formed by photolithography and etching. Further, polysilicon is deposited by the CVD method to a thickness that fills the contact hole 15. Next, a contact portion 16 is formed by an etch-back technique while leaving polysilicon only inside the contact hole 15. Then, the thickness of the second insulating film 14 is reduced to 500 nm to 100 nm by precision polishing, for example, polishing, and the surface of the second insulating film 14 and the surface of the contact portion 16 are flush with each other. It is formed on a smooth surface arranged in the plane of ^ ^.

Next, an oxide film (not shown) is formed on the back surface of the substrate 11 as shown in FIG. Thereafter, a P-type (100) silicon single crystal 35 of a single crystal semiconductor whose surface is precisely polished and flattened is applied to the surface of the second insulating film 14 and the surface of the contact portion 16. The heat treatment is performed in contact with the substrate. Then, it is bonded by Van der Waalska.

Then, a P-type (10-th) silicon single crystal 35

Precision polishing to 500 nm to l OOOnm. And The P-type 100) silicon single crystal 35 is formed into an island-shaped single crystal semiconductor pattern 17 by using a photolithography technique and an etching technique.

Next, as shown in FIG. 6, a 15-nm-thick oxide film that becomes a gate oxide film 19 is formed on the surface of the single-crystal semiconductor pattern 17 by a thermal oxidation method. Further, boron ions are implanted into the single crystal semiconductor pattern 17 by an ion implantation method. Subsequently, polysilicon for forming the gate electrode 20 and the gate electrode wiring 23 is deposited to a thickness of about 300 nm by the CVD method. In addition, high concentrations of phosphorus ions are introduced into the polysilicon by ion implantation. Then, a gate electrode 20, a gate oxide film 19, and a gate electrode wiring 23 are formed by a photolithography technique and an etching technique. Thereafter, arsenic is introduced at a high concentration into the single crystal semiconductor layer 17 by using the gate electrode 20 as a mask by ion implantation to form an N-type diffusion layer. This N-type diffusion layer forms a first source drain diffusion layer 21 and a second source drain diffusion layer 22.

Next, as shown in FIG. 6, an oxide film is deposited on the entire surface by a CVD method to form a third insulating film 24. Subsequently, contact holes 25 are formed by photolithography technology and etching technology. Thereafter, a polysilicon film having a thickness of 100 nm to 200 nm is deposited on the surface of the third insulating film 24 including the inside of the contact hole 25 by using the CVD method. Subsequently, high-concentration phosphorus is implanted into the polysilicon film using the ion implantation method. And the photolitho The polysilicon film is processed into the storage node electrode 27 by using the graphic technology and the etching technology. Subsequently, a silicon nitride film is deposited to a thickness of 6 nm to 10 nm on the entire surface on the storage node electrode 27 side by a CVD method to form a dielectric thin film 28. Further, a polysilicon film is deposited to a thickness of 20 O nm by a CVD method to form a plate electrode 29.

Next, as shown in FIG. 6, a boron ligated glass (BPSG) for forming the fourth insulating film 30 is formed on the entire surface of the plate electrode 29 side. Next, a contact hole (not shown) is formed by photolithography and etching. Next, an aluminum or aluminum alloy is deposited by a sputtering method. Then, a word line 31 is formed by a photolithography technique and an etching technique. Further, a passivation film 32 is formed on the entire surface, and the wafer process is completed. Industrial applicability

According to the first embodiment of the present invention, the source drain diffusion layer and the bit line are connected through the bit contact hole provided in the third insulating film. It is possible to set up only the event. Therefore, the capacity can be formed in an area having a sufficient capacitance, and the accumulated information is not destroyed by unnecessary charges.

Further, according to the second embodiment of the present invention, the source drain Since the 0 diffusion layer and the bit line are connected via the contact portion provided in the second insulating film, only the stack capacity can be provided on the surface of the third insulating film. Therefore, since the shock capacitor can be formed in an area having a sufficient capacitance, the stored information is not destroyed by unnecessary charges.

Also, in both of the first and second embodiments, it is possible to block the Alfma particles that are to be incident on the stack capacitor with each insulating film. Therefore, no soft error occurs, and the reliability of the semiconductor memory device can be improved.

Claims

Scope of request: 1 transistor 1 cano. In a semiconductor memory device with a screen type memory cell

Canon switching transistor. A semiconductor memory device characterized by being sandwiched between a silicon substrate and a bit line; (a) a capacitor substrate formed on a rigid substrate via a first insulating film;

(b) formed on the capacitor via a second insulating film, and formed on the capacitor via a conductive material formed in a first contact hole provided in the second insulating film; Connected transistors and

(c) formed on the transistor via a third insulating film, and provided on the third insulating film; and via the second contact hole provided on the third insulating film, Bit connected to the register

A semiconductor memory device having:

. A substrate formed of a rigid material;

A first insulating film formed on the substrate surface,

A capacitor formed on the surface of the first insulating film; a second insulating film formed on the entire surface on the capacitor side; and a contact portion provided on the second insulating film and connected to the capacitor. ,

An island-shaped single-crystal semiconductor pattern disposed on the surface of the second insulating film and connected to the connector; An oxide film disposed on the surface of the single crystal semiconductor pattern;

A gate electrode formed on the upper surface of the gate oxide film, and a single crystal semiconductor pattern formed by modifying the single crystal semiconductor pattern while being connected to one side of the gate oxide film and the contact portion. The first source drain diffusion layer

A second source drain diffusion layer formed by modifying the single crystal semiconductor pattern while being connected to the other side of the gate oxide film;

A third insulating film formed on the entire surface on the gate electrode side; and the second source via a bit contact hole provided on the surface of the third insulating film and provided in the third insulating film. A semiconductor memory device comprising a bit line connected to a drain diffusion layer.

4. (a) A bit line formed on a rigid substrate via a first insulating film;

(b) the bit line is formed on the bit line via a second insulating film, and via a conductive material formed in a first contact hole provided in the second insulating film; A transistor connected to

(c) a stack formed on the transistor via a third insulating film and connected to the transistor via a second connector hole provided in the third insulating film; Evening

A semiconductor memory device having:

5. a substrate formed of a rigid material; A first insulating film formed on the surface of the substrate; a bit line disposed on the surface of the first insulating film; a second insulating film formed on the entire surface on the bit line side; A contact portion provided on the film and connected to the bit line;

An island-shaped single crystal semiconductor pattern disposed on the surface of the second insulating film and connected to the contact portion; and a gate oxide film disposed on the surface of the single crystal semiconductor package. ,

A gate electrode formed on an upper surface of the gate oxide film, and a first source drain diffusion formed by modifying a region of the single crystal semiconductor pattern connected to one side of the gate oxide film Layers and

A second source drain diffusion layer formed by modifying a region of the single crystal semiconductor pattern connected to the other side of the gate oxide film and the contact portion;

A third insulating film formed on the entire surface on the side of the gate electrode; and a contact hole provided on a surface of the third insulating film and provided in the third insulating film to the first source drain diffusion layer. A semiconductor memory device characterized by comprising a stacked capacity connected thereto.

A method of manufacturing the semiconductor memory device, comprising: forming a first insulating film on a surface of a rigid substrate; forming a capacitor on the surface of the first insulating film; Forming a second insulating film on the entire surface, penetrating the second insulating film and connecting to the capacitor; Providing a contact portion, and forming the surface of the second insulating film and the surface of the contact portion in a planar state;

Attaching a single crystal semiconductor to the surface of the second insulating film while being connected to the contact portion;

Forming the single crystal semiconductor into an island-shaped single crystal semiconductor pattern;

Forming a gate oxide film and a gate electrode on the surface of the single crystal semiconductor pattern, introducing a conductive impurity into the single crystal semiconductor pattern on both sides of the gate oxide film, and connecting the single crystal semiconductor pattern to the contact portion; Forming a first source drain diffusion layer and a second source drain diffusion layer;

A third insulating film is formed on the entire surface on the side of the gate electrode, and a bit contact hole is provided through the third insulating film to reach the second source drain diffusion layer. Arranging a bit line connected to the second source drain diffusion layer. A method of manufacturing a semiconductor memory device, comprising:

A method for manufacturing the semiconductor memory device, comprising: forming a first insulating film on a surface of a rigid substrate; and disposing a bit line on a surface of the first insulating film; Forming a second insulating film on the entire surface on the contact line side, providing a contact portion penetrating through the second insulating film and connecting to the bit line, and contacting the second insulating film surface with the contact portion; Forming a flat surface with the surface;

While being connected to the contact portion, the second insulating film Attaching a single crystal semiconductor to the surface to form an island-shaped single crystal semiconductor pattern;

Forming a gate oxide film and a gate electrode on the surface of the single crystal semiconductor pattern; introducing a conductive impurity into the single crystal semiconductor pattern on both sides of the gate oxide film to form a first source drain diffusion; Forming a layer and a second source drain diffusion layer connected to the contact portion; forming a third insulating film on the entire surface on the side of the gate electrode; A contact hole penetrating the film and reaching the first source drain diffusion layer is provided, and a stack connected to the first source drain diffusion layer through the contact hole is provided. A method of manufacturing a semiconductor memory device, characterized by comprising a step of forming a cut capacity. Ii.