KR900017196A - 동적 메모리 셀을 구비한 반도체 메모리 장치 - Google Patents

동적 메모리 셀을 구비한 반도체 메모리 장치 Download PDF

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Publication number
KR900017196A
KR900017196A KR1019890004880A KR890004880A KR900017196A KR 900017196 A KR900017196 A KR 900017196A KR 1019890004880 A KR1019890004880 A KR 1019890004880A KR 890004880 A KR890004880 A KR 890004880A KR 900017196 A KR900017196 A KR 900017196A
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South Korea
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insulating layer
memory device
thickness
trench
region
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KR1019890004880A
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KR920005322B1 (en
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히로시 고따끼
야스까즈 이노우에
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세끼모또 다다히로
니뽄 덴끼 가부시끼가이샤
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Publication of KR900017196A publication Critical patent/KR900017196A/ko
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Publication of KR920005322B1 publication Critical patent/KR920005322B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92Capacitors having potential barriers
    • H01L29/94Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945Trench capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

동적 메모리 셀을 구비한 반도체 메모리 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (5)

  1. 제1도전형의 반도체 기판상에 형성된 다수의 동적 메모리 셀을 구비하는데, 상기 각 메모리 셀은 상기 반도체 기판의 표면에 형성되고, 상기 제1도전형에 대향한 제2도전형의 제1및 제2영역을 가진 게이트 전계효과 트랜지스터, 상기 제1 및 제2영역 사이의 상기 반도체 기판의 표면상에 형성된 게이트 절연층, 상기 게이트 전극의 표면을 피복하고, 제1두께를 가진 제1절연층 및 상기 게이트 절연층상에 형성된 게이트 전극과, 상기 제1절연층을 통해 상기 반도체 기판의 표면상에 형성된 제2절연층을 가진 기억 캐패시터를 포함하며, 상기 제2절연층은 상기 제1두께보다 큰 제2두께 상기 제1영역의 표면을 노출시킨 제1트렌치, 상기 제2절연층을 상기 트렌치의 측벽상에 형성되고, 상기 제1영역에 전기 접속된 제1도전층, 상기 제1도전층의 표면상에 형성된 유전 절연층 및 상기 유전 절연층의 표면상에 형성된 제2도전층을 가지는 것을 특징으로 하는 반도체 메모리장치.
  2. 제1항에 있어서, 상기 제2절연층이 상기 제2영역의 표면을 노출하기 위한 제2트렌치를 포함하며, 상기 메모리 소자가 상기 제2트렌치에 채워지며 상기 제2영역에 전기적으로 접속되는 전도 재료와, 상기 전도 재료에 접속된 디지트 라인을 구비하는 것을 특징으로 하는 반도체 메모리장치.
  3. 제1항에 있어서, 상기 제1 및 제2전도층이 다결정 실리콘으로 형성되는 것을 특징으로 하는 반도체 메모리장치.
  4. 제1항에 있어서, 상기 제2두께가 상기 제1두께보다 3배인 것을 특징으로 하는 반도체 메모리 장치.
  5. 제1항에 있어서, 상기 제1절연층이 실리콘 산화물로 형성되며 상기 제2절연층이 보론포스퍼러스(붕소인) 규산유리인 것을 특징으로 하는 반도체 메모리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8904880A 1988-04-13 1989-04-13 Semiconductor memory device having dynamic memory cell KR920005322B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-92328 1988-04-13
JP63092328A JP2723530B2 (ja) 1988-04-13 1988-04-13 ダイナミック型ランダムアクセスメモリ装置の製造方法

Publications (2)

Publication Number Publication Date
KR900017196A true KR900017196A (ko) 1990-11-15
KR920005322B1 KR920005322B1 (en) 1992-07-02

Family

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Family Applications (1)

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KR8904880A KR920005322B1 (en) 1988-04-13 1989-04-13 Semiconductor memory device having dynamic memory cell

Country Status (4)

Country Link
US (1) US5028990A (ko)
EP (1) EP0337436A3 (ko)
JP (1) JP2723530B2 (ko)
KR (1) KR920005322B1 (ko)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01290255A (ja) * 1988-05-18 1989-11-22 Toshiba Corp 半導体記憶装置およびその製造方法
US5180683A (en) * 1988-06-10 1993-01-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing stacked capacitor type semiconductor memory device
JPH03136276A (ja) * 1989-10-20 1991-06-11 Fujitsu Ltd ダイナミック型半導体記憶装置
US5202849A (en) * 1989-10-20 1993-04-13 Fujitsu Limited Dynamic semiconductor memory device
JP2501647B2 (ja) * 1989-12-08 1996-05-29 三菱電機株式会社 半導体記憶装置及びその製造方法
KR960002078B1 (ko) * 1989-12-29 1996-02-10 샤프 가부시끼가이샤 반도체메모리의 제조방법
JPH03229459A (ja) * 1990-02-05 1991-10-11 Nec Corp 半導体メモリおよびその製造方法
JP2519569B2 (ja) * 1990-04-27 1996-07-31 三菱電機株式会社 半導体記憶装置およびその製造方法
FR2663786A1 (fr) * 1990-06-21 1991-12-27 Samsung Electronics Co Ltd Procede de fabrication de condensateurs dans une cellule dram.
DE69122192T2 (de) * 1990-06-26 1997-04-24 Sharp Kk Halbleiterspeichereinrichtung
US5241205A (en) * 1990-06-26 1993-08-31 Sharp Kabushiki Kaisha Semiconductor memory device
US5256892A (en) * 1990-06-29 1993-10-26 Nec Corporation Semiconductor memory device wherein gate electrode thickness is greater in the memory cells than in the peripheral cells
KR940001426B1 (ko) * 1991-03-27 1994-02-23 삼성전자 주식회사 고집적 반도체 메모리장치 및 그 제조방법
KR930009131B1 (ko) * 1991-04-24 1993-09-23 삼성전자 주식회사 초고집적 반도체 메모리장치의 제조방법
KR940006587B1 (ko) * 1991-05-23 1994-07-22 삼성전자 주식회사 디램셀의 캐패시터 제조방법
JPH11297960A (ja) * 1998-04-16 1999-10-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
DE69226223T2 (de) * 1991-08-21 1998-12-24 Sgs Thomson Microelectronics Kontaktausrichtung für Festwertspeicher
KR930015002A (ko) * 1991-12-18 1993-07-23 김광호 반도체 메모리 장치 및 그 제조방법
US5126916A (en) * 1991-12-20 1992-06-30 Industrial Technology Research Institute Stacked capacitor dram cell and method of fabricating
KR100244172B1 (ko) * 1992-01-14 2000-02-01 김영환 디램 셀 제조방법
US5364814A (en) * 1992-07-09 1994-11-15 Micron Technology, Inc. Germanium implanted stacked capacitor cell
WO1996027901A1 (en) * 1995-03-07 1996-09-12 Micron Technology, Inc. Improved semiconductor contacts to thin conductive layers
US6150211A (en) 1996-12-11 2000-11-21 Micron Technology, Inc. Methods of forming storage capacitors in integrated circuitry memory cells and integrated circuitry
GB2324408A (en) * 1997-01-21 1998-10-21 United Microelectronics Corporation Forming DRAM cells
US5970340A (en) 1997-06-24 1999-10-19 Micron Technology, Inc. Method for making semiconductor device incorporating an electrical contact to an internal conductive layer
TW365065B (en) * 1997-07-19 1999-07-21 United Microelectronics Corp Embedded memory structure and manufacturing method thereof
GB2331839B (en) * 1997-07-19 1999-10-13 United Microelectronics Corp Process and structure for embedded dram
NL1007804C2 (nl) * 1997-12-16 1999-06-17 United Microelectronics Corp Werkwijze voor het vervaardigen van een geïntegreerde circuit-inrichting met ingebedde DRAM circuits en logische circuits op een enkel substraat.
US6673671B1 (en) 1998-04-16 2004-01-06 Renesas Technology Corp. Semiconductor device, and method of manufacturing the same
KR100301370B1 (ko) * 1998-04-29 2001-10-27 윤종용 디램셀커패시터의제조방법
GB2337633B (en) * 1998-05-20 2003-04-02 Mitel Corp Method of forming capacitors in a semiconductor device
US6271596B1 (en) * 1999-01-12 2001-08-07 Agere Systems Guardian Corp. Damascene capacitors for integrated circuits
US6750495B1 (en) * 1999-05-12 2004-06-15 Agere Systems Inc. Damascene capacitors for integrated circuits
US6429123B1 (en) * 2000-10-04 2002-08-06 Vanguard International Semiconductor Corporation Method of manufacturing buried metal lines having ultra fine features
US6760498B2 (en) * 2001-05-17 2004-07-06 Sioptical, Inc. Arrayed waveguide grating, and method of making same
DE102004004584A1 (de) * 2004-01-29 2005-08-25 Infineon Technologies Ag Halbleiterspeicherzelle sowie zugehöriges Herstellungsverfahren

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0673368B2 (ja) * 1985-01-31 1994-09-14 富士通株式会社 半導体記憶装置およびその製造方法
JP2621181B2 (ja) * 1987-06-12 1997-06-18 日本電気株式会社 Mis型半導体記憶装置
JPS6441262A (en) * 1987-08-07 1989-02-13 Hitachi Ltd Memory cell

Also Published As

Publication number Publication date
EP0337436A3 (en) 1990-04-18
EP0337436A2 (en) 1989-10-18
JP2723530B2 (ja) 1998-03-09
US5028990A (en) 1991-07-02
JPH01262658A (ja) 1989-10-19
KR920005322B1 (en) 1992-07-02

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