DE69226223T2 - Kontaktausrichtung für Festwertspeicher - Google Patents

Kontaktausrichtung für Festwertspeicher

Info

Publication number
DE69226223T2
DE69226223T2 DE69226223T DE69226223T DE69226223T2 DE 69226223 T2 DE69226223 T2 DE 69226223T2 DE 69226223 T DE69226223 T DE 69226223T DE 69226223 T DE69226223 T DE 69226223T DE 69226223 T2 DE69226223 T2 DE 69226223T2
Authority
DE
Germany
Prior art keywords
read
memory
contact alignment
alignment
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69226223T
Other languages
English (en)
Other versions
DE69226223D1 (de
Inventor
Frank Randolph Bryant
Tsiu Chiu Chan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69226223D1 publication Critical patent/DE69226223D1/de
Application granted granted Critical
Publication of DE69226223T2 publication Critical patent/DE69226223T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Non-Volatile Memory (AREA)
DE69226223T 1991-08-21 1992-08-20 Kontaktausrichtung für Festwertspeicher Expired - Fee Related DE69226223T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US74829091A 1991-08-21 1991-08-21

Publications (2)

Publication Number Publication Date
DE69226223D1 DE69226223D1 (de) 1998-08-20
DE69226223T2 true DE69226223T2 (de) 1998-12-24

Family

ID=25008824

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69226223T Expired - Fee Related DE69226223T2 (de) 1991-08-21 1992-08-20 Kontaktausrichtung für Festwertspeicher

Country Status (4)

Country Link
US (2) US5376571A (de)
EP (1) EP0528690B1 (de)
JP (1) JPH0685277A (de)
DE (1) DE69226223T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7071060B1 (en) * 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
ES2154291T3 (es) * 1992-12-09 2001-04-01 Discovery Communicat Inc Controlador de red para sistemas de distribucion de programas de television por cable.
JP3224907B2 (ja) * 1993-06-08 2001-11-05 株式会社東芝 不揮発性半導体記憶装置
FR2711275B1 (fr) * 1993-10-15 1996-10-31 Intel Corp Procédé automatiquement aligné de contact en fabrication de semi-conducteurs et dispositifs produits.
US5702979A (en) * 1994-05-31 1997-12-30 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5945738A (en) * 1994-05-31 1999-08-31 Stmicroelectronics, Inc. Dual landing pad structure in an integrated circuit
US5956615A (en) * 1994-05-31 1999-09-21 Stmicroelectronics, Inc. Method of forming a metal contact to landing pad structure in an integrated circuit
JP4156044B2 (ja) * 1994-12-22 2008-09-24 エスティーマイクロエレクトロニクス，インコーポレイテッド 集積回路におけるランディングパッド構成体の製造方法
US5705427A (en) * 1994-12-22 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
JP3542189B2 (ja) * 1995-03-08 2004-07-14 株式会社ルネサステクノロジ 半導体装置の製造方法及び半導体装置
KR19980014258A (ko) * 1996-08-09 1998-05-25 김주용 메모리 셀 어레이
JP3548834B2 (ja) * 1996-09-04 2004-07-28 沖電気工業株式会社 不揮発性半導体メモリの製造方法
US5854127A (en) * 1997-03-13 1998-12-29 Micron Technology, Inc. Method of forming a contact landing pad
TW471116B (en) * 1999-01-22 2002-01-01 United Microelectronics Corp Contact isolation structure and the manufacturing method thereof
US6821847B2 (en) * 2001-10-02 2004-11-23 Mosel Vitelic, Inc. Nonvolatile memory structures and fabrication methods
US6461905B1 (en) * 2002-02-22 2002-10-08 Advanced Micro Devices, Inc. Dummy gate process to reduce the Vss resistance of flash products
US8247861B2 (en) * 2007-07-18 2012-08-21 Infineon Technologies Ag Semiconductor device and method of making same
US20140015031A1 (en) * 2012-07-12 2014-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method for Memory Device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4935380A (en) * 1987-08-04 1990-06-19 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing semiconductor device
JP2723530B2 (ja) * 1988-04-13 1998-03-09 日本電気株式会社 ダイナミック型ランダムアクセスメモリ装置の製造方法
FR2638285B1 (fr) * 1988-10-25 1992-06-19 Commissariat Energie Atomique Circuit integre a haute densite d'integration tel que memoire eprom et procede d'obtention correspondant
US5113238A (en) * 1989-01-06 1992-05-12 Wang Chen Chin Contactless non-volatile memory array cells
FR2642900B1 (fr) * 1989-01-17 1991-05-10 Sgs Thomson Microelectronics Procede de fabrication de circuits integres a transistors de memoire eprom et a transistors logiques
KR920005453B1 (ko) * 1989-05-13 1992-07-04 현대전자산업 주식회사 반도체 접속장치 형성방법
EP0405850A3 (de) * 1989-06-30 1991-03-13 AT&T Corp. Dielektrikum-Herstellungsverfahren und dadurch hergestellte Komponente
JPH0783066B2 (ja) * 1989-08-11 1995-09-06 株式会社東芝 半導体装置の製造方法
IT1236601B (it) * 1989-12-22 1993-03-18 Sgs Thomson Microelectronics Dispositivo a semiconduttore integrato di tipo eprom con connessioni metalliche di source e procedimento per la sua fabbricazione.
JP2825585B2 (ja) * 1990-01-29 1998-11-18 株式会社日立製作所 半導体集積回路装置及びその製造方法
JP2524863B2 (ja) * 1990-05-02 1996-08-14 三菱電機株式会社 半導体装置およびその製造方法
JP2893894B2 (ja) * 1990-08-15 1999-05-24 日本電気株式会社 不揮発性メモリ及びその製造方法
US5060190A (en) * 1990-09-18 1991-10-22 Industrial Technology Research Institute Read only memory with write operation using mask
US5231043A (en) * 1991-08-21 1993-07-27 Sgs-Thomson Microelectronics, Inc. Contact alignment for integrated circuits

Also Published As

Publication number Publication date
US5448091A (en) 1995-09-05
EP0528690A1 (de) 1993-02-24
DE69226223D1 (de) 1998-08-20
US5376571A (en) 1994-12-27
EP0528690B1 (de) 1998-07-15
JPH0685277A (ja) 1994-03-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee