DE69120301D1 - Speicherprüfgerät - Google Patents

Speicherprüfgerät

Info

Publication number
DE69120301D1
DE69120301D1 DE69120301T DE69120301T DE69120301D1 DE 69120301 D1 DE69120301 D1 DE 69120301D1 DE 69120301 T DE69120301 T DE 69120301T DE 69120301 T DE69120301 T DE 69120301T DE 69120301 D1 DE69120301 D1 DE 69120301D1
Authority
DE
Germany
Prior art keywords
memory tester
tester
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69120301T
Other languages
English (en)
Other versions
DE69120301T2 (de
Inventor
Toshimi Oosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Application granted granted Critical
Publication of DE69120301D1 publication Critical patent/DE69120301D1/de
Publication of DE69120301T2 publication Critical patent/DE69120301T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
DE69120301T 1990-01-12 1991-01-02 Speicherprüfgerät Expired - Fee Related DE69120301T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004788A JP2915945B2 (ja) 1990-01-12 1990-01-12 メモリ試験装置

Publications (2)

Publication Number Publication Date
DE69120301D1 true DE69120301D1 (de) 1996-07-25
DE69120301T2 DE69120301T2 (de) 1996-12-05

Family

ID=11593527

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120301T Expired - Fee Related DE69120301T2 (de) 1990-01-12 1991-01-02 Speicherprüfgerät

Country Status (5)

Country Link
US (1) US5214654A (de)
EP (1) EP0437217B1 (de)
JP (1) JP2915945B2 (de)
KR (1) KR950000343B1 (de)
DE (1) DE69120301T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2577120Y2 (ja) * 1993-04-15 1998-07-23 株式会社アドバンテスト 過剰パルス印加の禁止回路
JP3186359B2 (ja) * 1993-07-28 2001-07-11 安藤電気株式会社 物理アドレス変換回路
US5712999A (en) * 1993-11-30 1998-01-27 Texas Instruments Address generator employing selective merge of two independent addresses
US5506959A (en) * 1994-08-04 1996-04-09 Telecommunication Research Laboratories Method and apparatus for testing electronic memories for the presence of multiple cell coupling faults
WO2004097840A1 (ja) * 1995-09-06 2004-11-11 Osamu Yamada Sdram用テストパターン発生装置及び方法
US6463081B1 (en) * 1998-04-07 2002-10-08 United Microelectronics Corp. Method and apparatus for fast rotation
US6389525B1 (en) 1999-01-08 2002-05-14 Teradyne, Inc. Pattern generator for a packet-based memory tester
EP1026696B1 (de) 1999-02-02 2005-07-06 Fujitsu Limited Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung
US6434503B1 (en) * 1999-12-30 2002-08-13 Infineon Technologies Richmond, Lp Automated creation of specific test programs from complex test programs
US6608779B1 (en) * 2000-06-02 2003-08-19 Intel Corporation Method and apparatus for low power memory
US6671844B1 (en) * 2000-10-02 2003-12-30 Agilent Technologies, Inc. Memory tester tests multiple DUT's per test site
KR100379542B1 (ko) * 2000-11-23 2003-04-10 주식회사 하이닉스반도체 반도체 메모리소자의 테스트장치
US20030167428A1 (en) * 2001-04-13 2003-09-04 Sun Microsystems, Inc ROM based BIST memory address translation
US7656893B2 (en) * 2002-08-07 2010-02-02 Broadcom Corporation System and method for implementing auto-configurable default polarity
US6925588B2 (en) * 2002-12-23 2005-08-02 Lsi Logic Corporation Methods and apparatus for testing data lines
US7328304B2 (en) * 2004-02-27 2008-02-05 Intel Corporation Interface for a block addressable mass storage system
WO2009141849A1 (ja) * 2008-05-21 2009-11-26 株式会社アドバンテスト パターン発生器
JP5186587B1 (ja) * 2011-09-29 2013-04-17 株式会社アドバンテスト 試験装置および試験方法
JP6046012B2 (ja) * 2013-09-11 2016-12-14 株式会社東芝 Ｂｉｓｔ回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414665A (en) * 1979-11-21 1983-11-08 Nippon Telegraph & Telephone Public Corp. Semiconductor memory device test apparatus
JP2527935B2 (ja) * 1986-05-19 1996-08-28 株式会社 アドバンテスト 半導体メモリ試験装置
DE3773773D1 (de) * 1986-06-25 1991-11-21 Nec Corp Pruefschaltung fuer eine speichereinrichtung mit willkuerlichem zugriff.
JPH01184700A (ja) * 1988-01-11 1989-07-24 Advantest Corp メモリ試験装置
US4866676A (en) * 1988-03-24 1989-09-12 Motorola, Inc. Testing arrangement for a DRAM with redundancy
JP2719684B2 (ja) * 1988-05-23 1998-02-25 株式会社アドバンテスト 遅延発生装置
JP2779538B2 (ja) * 1989-04-13 1998-07-23 三菱電機株式会社 半導体集積回路メモリのためのテスト信号発生器およびテスト方法

Also Published As

Publication number Publication date
KR950000343B1 (ko) 1995-01-13
EP0437217A3 (en) 1992-04-08
JPH03210483A (ja) 1991-09-13
EP0437217A2 (de) 1991-07-17
DE69120301T2 (de) 1996-12-05
JP2915945B2 (ja) 1999-07-05
US5214654A (en) 1993-05-25
EP0437217B1 (de) 1996-06-19
KR910014951A (ko) 1991-08-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee