KR900013658A - Bi-CMOS반도체장치 - Google Patents

Bi-CMOS반도체장치 Download PDF

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Publication number
KR900013658A
KR900013658A KR1019900002073A KR900002073A KR900013658A KR 900013658 A KR900013658 A KR 900013658A KR 1019900002073 A KR1019900002073 A KR 1019900002073A KR 900002073 A KR900002073 A KR 900002073A KR 900013658 A KR900013658 A KR 900013658A
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conductive
semiconductor device
well region
mos transistor
buried layer
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KR1019900002073A
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KR970005146B1 (ko
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다케오 마에다
슈소 후지이
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아오이 죠이치
가부시키가이샤 도시바
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Priority to KR1019940012349A priority Critical patent/KR950009798B1/ko
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Publication of KR970005146B1 publication Critical patent/KR970005146B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

Bi-CMOS반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도(A)~제1도(J)는 본발명의 제1실시예에 따른 Bi-CMOS반도체장치의 제조공정을 나타낸 단면도.

Claims (11)

  1. 바이폴라 트랜지스터와 상보형 MOS트랜지스터가 1칩상에 혼재되어 있는 Bi-CMOS반도체장치에 있어서, 제1도전형 반도체기판(10)과, 이 반도체기판(10)에 형성된 제2도전형 매립층(13), 이 매립층(13)상에 형성된 제1도전형 웰영역(16), 이 웰영역(16) 중 소정의 제1영역에 형성되는 제2도전채널형 제1MOS트랜지스터, 상기 매립층(13)과 공동으로 상기 웰영역(16)의 제1영역을 둘러싸도록 형성된 제2도전형 포위층(22)을 구비하여 구성된 것을 특징으로 하는 Bi-CMOS반도체장치.
  2. 제1항에 있어서, 상기 제1도전형 웰영역(16)중 소정의 제2영역에 형성되는 제2도전챈널형 제2MOS트랜지스터가 구비된 것을 특징으로 하는 Bi-CMOS반도체장치.
  3. 제2항에 있어서, 상기 제1도전형 웰영역(16)중 제1영역 및 제2영역에 서로 다른 값의 제1,제2바이어스전압이 공급되는 것을 특징으로 하는 Bi-CMOS반도체장치.
  4. 제3항에 있어서, 상기 반도체장치가 메모리장치이고, 상기 제1MOS 트랜지스터가 메모리셀을 구성하기 위해 사용되며, 상기 제2MOS트랜지스터가 주변회로를 구성하기 위해 사용되는 것을 특징으로 하는 Bi-CMOS반도체장치.
  5. 바이폴라 트랜지스터와 상보형 MOS트랜지스터가 1칩상에 혼재되어 있는 Bi-CMOS반도체장치에 있어서, 제1도전형 반도체기판(10)과, 이 반도체기판(10)에 형성된 제1도전형 매립층(9), 이 매립층(9)상에 형성된 제1도전형 웰영역(16). 이 웰영역(16)중 소정의 제1영역에 형성되는 제2도전챈널형 제1MOS트랜지스터, 상기 매립층(9) 및 웰영역(16)의 소정의 제1영역을 둘러싸도록 형성된 제2도전형 포위칭(1,15)을 구비하여 구성된 것을 특징으로 하는 Bi-CMOS반도체장치.
  6. 제5항에 있어서, 상기 제1도전형 웰영역(16)중 소정의 제2영역에 형성되는 제2도전챈널형 제2MOS트랜지스터가 구비된 것을 특징으로 하는 Bi-CMOS반도체장치.
  7. 제6항에 있어서, 상기 제1도전형 웰영역(16)중 제1영역 및 제2영역에 서로 다른 값의 제1,제2바이어스전압이 공급되는 것을 특징으로 하는 Bi-CMOS반도체장치.
  8. 제7항에 있어서, 상기 반도체장치가 메모리장치고, 상기 제1MOS트랜지스터가 메모리셀을 구성하기 위해 사용되며, 상기 제2MOS트랜지스터가 주변회로를 구성하기 위해 사용되는 것을 특징으로 하는 Bi-CMOS반도체장치.
  9. 제1도전형 반도체기판(19)과, 이 반도체 기판(10)에 형성된 제1도전형 매립층(13), 이 매립층(13)을 상기 반도체기판(10)으로부터 전기적으로 분리시키기위해 매립층(13)을 둘러싸도록 상기 반도체기판(10)에 형성된 제2도전형 포위칭(3,9)이 매립층(13)상에 형성된 제1도전형 제1웰영역(14), 이 웰영역(14)에 인접하게 형성된 제2도전형 제2웰영역(16), 상기 제1웰영역(14)에 형성된 바이폴라 트랜지스터, 상기 제2웰영역(16)에 형성된 제1도전챈널형 1MOS트랜지스터를 구비하여 구성된 것을 특징으로 하는 Bi-CMOS반도체장치.
  10. 제9항에 있어서, 상기 제2웰영역(16)은 상기 포위층(3,9)과 공동으로 상기 제1웰영역(14)을 둘러싸도록 형성되어 있는 것을 특징으로 하는 Bi-CMOS반도체장치.
  11. 제9항에 있어서, 상기 반도체장치가 메모리장치고, 상기 제1MOS트랜지스터가 메모리셀을 구성하기 위해 사용되며, 상기 바이폴라 트랜지스터가 주변회로를 구성하기 위해 사용되는 것을 특징으로 하는 Bi-CMOS반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900002073A 1989-02-20 1990-02-20 Bi-CMOS 반도체장치 KR970005146B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940012349A KR950009798B1 (ko) 1989-02-20 1994-06-02 Bi-CMOS 반도체장치의 제조방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-39816 1989-02-20
JP1039816A JP2509690B2 (ja) 1989-02-20 1989-02-20 半導体装置

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KR970005146B1 KR970005146B1 (ko) 1997-04-12

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US (1) US5075752A (ko)
EP (1) EP0384396B1 (ko)
JP (1) JP2509690B2 (ko)
KR (1) KR970005146B1 (ko)
DE (1) DE69033321T2 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04363059A (ja) * 1990-08-23 1992-12-15 Seiko Epson Corp 半導体装置およびその製造方法
JP2609753B2 (ja) * 1990-10-17 1997-05-14 株式会社東芝 半導体装置
US5075571A (en) * 1991-01-02 1991-12-24 International Business Machines Corp. PMOS wordline boost cricuit for DRAM
SG45211A1 (en) * 1992-01-09 1998-01-16 Ibm Double grid and double well substrate plate trench dram cell array
US5264716A (en) * 1992-01-09 1993-11-23 International Business Machines Corporation Diffused buried plate trench dram cell array
JPH088268A (ja) * 1994-06-21 1996-01-12 Mitsubishi Electric Corp バイポーラトランジスタを有する半導体装置およびその製造方法
US5885880A (en) * 1994-09-19 1999-03-23 Sony Corporation Bipolar transistor device and method for manufacturing the same
KR100190008B1 (ko) * 1995-12-30 1999-06-01 윤종용 반도체 장치의 정전하 보호 장치
US5858828A (en) * 1997-02-18 1999-01-12 Symbios, Inc. Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor
US6927460B1 (en) 2002-02-15 2005-08-09 Fairchild Semiconductor Corporation Method and structure for BiCMOS isolated NMOS transistor
JP2005085349A (ja) * 2003-09-08 2005-03-31 Matsushita Electric Ind Co Ltd 半導体記憶装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5939904B2 (ja) * 1978-09-28 1984-09-27 株式会社東芝 半導体装置
US4311532A (en) * 1979-07-27 1982-01-19 Harris Corporation Method of making junction isolated bipolar device in unisolated IGFET IC
JPS58192359A (ja) * 1982-05-07 1983-11-09 Hitachi Ltd 半導体装置
JPS6035558A (ja) * 1983-08-08 1985-02-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
CN1004736B (zh) * 1984-10-17 1989-07-05 株式会社日立制作所 互补半导体器件
JPH073811B2 (ja) * 1985-04-12 1995-01-18 株式会社日立製作所 半導体記憶装置
JPS61281545A (ja) * 1985-06-06 1986-12-11 Fuji Electric Co Ltd バイポ−ラ・ｃｍｏｓ半導体装置
GB2186117B (en) * 1986-01-30 1989-11-01 Sgs Microelettronica Spa Monolithically integrated semiconductor device containing bipolar junction,cmosand dmos transistors and low leakage diodes and a method for its fabrication
JP2523506B2 (ja) * 1986-06-25 1996-08-14 株式会社日立製作所 半導体装置
JPS63292666A (ja) * 1987-05-25 1988-11-29 Nec Corp 半導体装置の製造方法
US4825275A (en) * 1987-05-28 1989-04-25 Texas Instruments Incorporated Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias
JPS63304657A (ja) * 1987-06-04 1988-12-12 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
DE69033321T2 (de) 2000-03-02
EP0384396B1 (en) 1999-10-13
JP2509690B2 (ja) 1996-06-26
EP0384396A3 (en) 1992-09-09
DE69033321D1 (de) 1999-11-18
EP0384396A2 (en) 1990-08-29
JPH02219262A (ja) 1990-08-31
KR970005146B1 (ko) 1997-04-12
US5075752A (en) 1991-12-24

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