DE69033321D1 - Bi CMOS-Halbleiteranordnung mit in isolierten Bereichen angeordneten Speicherzellen - Google Patents

Bi CMOS-Halbleiteranordnung mit in isolierten Bereichen angeordneten Speicherzellen

Info

Publication number
DE69033321D1
DE69033321D1 DE69033321T DE69033321T DE69033321D1 DE 69033321 D1 DE69033321 D1 DE 69033321D1 DE 69033321 T DE69033321 T DE 69033321T DE 69033321 T DE69033321 T DE 69033321T DE 69033321 D1 DE69033321 D1 DE 69033321D1
Authority
DE
Germany
Prior art keywords
memory cells
cells arranged
semiconductor arrangement
isolated regions
cmos semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033321T
Other languages
English (en)
Other versions
DE69033321T2 (de
Inventor
Takeo Maeda
Syuso Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69033321D1 publication Critical patent/DE69033321D1/de
Publication of DE69033321T2 publication Critical patent/DE69033321T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
  • Dram (AREA)
DE69033321T 1989-02-20 1990-02-20 Bi CMOS-Halbleiteranordnung mit in isolierten Bereichen angeordneten Speicherzellen Expired - Fee Related DE69033321T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1039816A JP2509690B2 (ja) 1989-02-20 1989-02-20 半導体装置

Publications (2)

Publication Number Publication Date
DE69033321D1 true DE69033321D1 (de) 1999-11-18
DE69033321T2 DE69033321T2 (de) 2000-03-02

Family

ID=12563496

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033321T Expired - Fee Related DE69033321T2 (de) 1989-02-20 1990-02-20 Bi CMOS-Halbleiteranordnung mit in isolierten Bereichen angeordneten Speicherzellen

Country Status (5)

Country Link
US (1) US5075752A (de)
EP (1) EP0384396B1 (de)
JP (1) JP2509690B2 (de)
KR (1) KR970005146B1 (de)
DE (1) DE69033321T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04363059A (ja) * 1990-08-23 1992-12-15 Seiko Epson Corp 半導体装置およびその製造方法
JP2609753B2 (ja) * 1990-10-17 1997-05-14 株式会社東芝 半導体装置
US5075571A (en) * 1991-01-02 1991-12-24 International Business Machines Corp. PMOS wordline boost cricuit for DRAM
EP0550894B1 (de) * 1992-01-09 1999-08-04 International Business Machines Corporation Matrix von Graben-DRAM-Zellen
US5264716A (en) * 1992-01-09 1993-11-23 International Business Machines Corporation Diffused buried plate trench dram cell array
JPH088268A (ja) * 1994-06-21 1996-01-12 Mitsubishi Electric Corp バイポーラトランジスタを有する半導体装置およびその製造方法
US5885880A (en) * 1994-09-19 1999-03-23 Sony Corporation Bipolar transistor device and method for manufacturing the same
KR100190008B1 (ko) * 1995-12-30 1999-06-01 윤종용 반도체 장치의 정전하 보호 장치
US5858828A (en) * 1997-02-18 1999-01-12 Symbios, Inc. Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor
US6927460B1 (en) 2002-02-15 2005-08-09 Fairchild Semiconductor Corporation Method and structure for BiCMOS isolated NMOS transistor
JP2005085349A (ja) * 2003-09-08 2005-03-31 Matsushita Electric Ind Co Ltd 半導体記憶装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5939904B2 (ja) * 1978-09-28 1984-09-27 株式会社東芝 半導体装置
US4311532A (en) * 1979-07-27 1982-01-19 Harris Corporation Method of making junction isolated bipolar device in unisolated IGFET IC
JPS58192359A (ja) * 1982-05-07 1983-11-09 Hitachi Ltd 半導体装置
JPS6035558A (ja) * 1983-08-08 1985-02-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
CN1004736B (zh) * 1984-10-17 1989-07-05 株式会社日立制作所 互补半导体器件
JPH073811B2 (ja) * 1985-04-12 1995-01-18 株式会社日立製作所 半導体記憶装置
JPS61281545A (ja) * 1985-06-06 1986-12-11 Fuji Electric Co Ltd バイポ−ラ・ｃｍｏｓ半導体装置
GB2186117B (en) * 1986-01-30 1989-11-01 Sgs Microelettronica Spa Monolithically integrated semiconductor device containing bipolar junction,cmosand dmos transistors and low leakage diodes and a method for its fabrication
JP2523506B2 (ja) * 1986-06-25 1996-08-14 株式会社日立製作所 半導体装置
JPS63292666A (ja) * 1987-05-25 1988-11-29 Nec Corp 半導体装置の製造方法
US4825275A (en) * 1987-05-28 1989-04-25 Texas Instruments Incorporated Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias
JPS63304657A (ja) * 1987-06-04 1988-12-12 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
KR970005146B1 (ko) 1997-04-12
JPH02219262A (ja) 1990-08-31
JP2509690B2 (ja) 1996-06-26
KR900013658A (ko) 1990-09-06
EP0384396A3 (de) 1992-09-09
US5075752A (en) 1991-12-24
DE69033321T2 (de) 2000-03-02
EP0384396B1 (de) 1999-10-13
EP0384396A2 (de) 1990-08-29

Similar Documents

Publication Publication Date Title
DE3571534D1 (en) Semiconductor integrated circuit with cmos gate array
DE69328639D1 (de) Halbleiterspeicheranordnung mit Ersatzspeicherzellen
DE3584142D1 (de) Integrierte halbleiterschaltungsanordnung mit eingebauten speichern.
DE3886114D1 (de) Halbleiterspeichergerät mit redundanter Speicherzellenmatrix.
DE69124291D1 (de) Halbleiterspeicher mit verbesserter Leseanordnung
DE69107808D1 (de) Festkörper-Speichermodule und Speicheranordnungen mit solchen Modulen.
DE69222589D1 (de) Nichtlöschbarer Halbleiterspeicher mit Reihendecoder
EP0453959A3 (en) Semiconductor memory cell
DE3788487D1 (de) Integrierte Schaltung mit Speicherselbstprüfung.
DE68920699D1 (de) Speicherzelle und Leseschaltung.
DE69328342D1 (de) Halbleiterspeicherzelle
DE69215707D1 (de) Halbleiter-Speicherzelle
GB2263016B (en) Hall effect semiconductor memory cell
DE3689004D1 (de) Halbleiterspeicherzelle.
GB2209858B (en) Semiconductor memory device with redundant memory cells
DE69228399D1 (de) Speicherzellenmatrix der Multiporthalbleiterspeicheranordnungstype
DE69033321D1 (de) Bi CMOS-Halbleiteranordnung mit in isolierten Bereichen angeordneten Speicherzellen
DE3767729D1 (de) Assoziativspeicherzelle.
DE69220465D1 (de) Halbleiteranordnung mit Speicherzelle
DE3583113D1 (de) Integrierte halbleiterschaltungsanordnung in polycell-technik.
DE69025516D1 (de) Halbleiter-Speichergerät mit redundanten Speicherzellen
DE69522545D1 (de) Halbleiterspeicheranordnung mit eingebauten Redundanzspeicherzellen
DE3879766D1 (de) Halbleiter speicherzelle.
DE69124010D1 (de) Halbleiterspeicherzelle
DE3781631D1 (de) Halbleiterspeichervorrichtung mit verbesserter zellenanordnung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee