DE3583113D1 - Integrierte halbleiterschaltungsanordnung in polycell-technik. - Google Patents

Integrierte halbleiterschaltungsanordnung in polycell-technik.

Info

Publication number
DE3583113D1
DE3583113D1 DE8585114225T DE3583113T DE3583113D1 DE 3583113 D1 DE3583113 D1 DE 3583113D1 DE 8585114225 T DE8585114225 T DE 8585114225T DE 3583113 T DE3583113 T DE 3583113T DE 3583113 D1 DE3583113 D1 DE 3583113D1
Authority
DE
Germany
Prior art keywords
polycell
technology
circuit arrangement
semiconductor circuit
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585114225T
Other languages
English (en)
Inventor
Hitoshi Kondoh
Akihiro Sueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3583113D1 publication Critical patent/DE3583113D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8585114225T 1984-11-09 1985-11-08 Integrierte halbleiterschaltungsanordnung in polycell-technik. Expired - Lifetime DE3583113D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59235192A JPH0644593B2 (ja) 1984-11-09 1984-11-09 半導体集積回路装置

Publications (1)

Publication Number Publication Date
DE3583113D1 true DE3583113D1 (de) 1991-07-11

Family

ID=16982439

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585114225T Expired - Lifetime DE3583113D1 (de) 1984-11-09 1985-11-08 Integrierte halbleiterschaltungsanordnung in polycell-technik.

Country Status (4)

Country Link
US (1) US4716452A (de)
EP (1) EP0182222B1 (de)
JP (1) JPH0644593B2 (de)
DE (1) DE3583113D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3584102D1 (de) * 1984-03-08 1991-10-24 Toshiba Kawasaki Kk Integrierte halbleiterschaltungsvorrichtung.
US4742019A (en) * 1985-10-30 1988-05-03 International Business Machines Corporation Method for forming aligned interconnections between logic stages
JPH073840B2 (ja) * 1987-08-31 1995-01-18 株式会社東芝 半導体集積回路
US5014110A (en) * 1988-06-03 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Wiring structures for semiconductor memory device
EP0387812A3 (de) * 1989-03-14 1992-08-05 Fujitsu Limited Bipolarer integrierter Schaltkreis mit einer Einheitsblock-Struktur
JPH04127452A (ja) * 1989-06-30 1992-04-28 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH0410624A (ja) * 1990-04-27 1992-01-14 Hitachi Ltd 半導体集積回路
JPH04116951A (ja) * 1990-09-07 1992-04-17 Fujitsu Ltd 半導体集積回路
JP2714723B2 (ja) * 1991-03-15 1998-02-16 シャープ株式会社 半導体集積回路装置の製造方法
DE4328474C2 (de) * 1993-08-24 1996-09-12 Gold Star Electronics Mehrschichtverbindungsstruktur für eine Halbleitereinrichtung
JPH08330434A (ja) * 1994-12-09 1996-12-13 Mitsubishi Electric Corp 半導体集積回路装置およびその配置配線方法並びにレイアウト方法
JPH10284605A (ja) * 1997-04-08 1998-10-23 Mitsubishi Electric Corp 半導体集積回路およびセルベース方式によりレイアウト設計された半導体集積回路
JP2000269339A (ja) 1999-03-16 2000-09-29 Toshiba Corp 半導体集積回路装置とその配線配置方法
JP4364226B2 (ja) * 2006-09-21 2009-11-11 株式会社東芝 半導体集積回路

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921282A (en) * 1971-02-16 1975-11-25 Texas Instruments Inc Insulated gate field effect transistor circuits and their method of fabrication
US3844831A (en) * 1972-10-27 1974-10-29 Ibm Forming a compact multilevel interconnection metallurgy system for semi-conductor devices
JPS51139286A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Multi-layer wiring pattern
JPS5816338B2 (ja) * 1975-07-29 1983-03-30 株式会社東芝 ハンドウタイソウチ
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
JPS5387A (en) * 1976-06-24 1978-01-05 Toshiba Corp Automatic design system
US4249193A (en) * 1978-05-25 1981-02-03 International Business Machines Corporation LSI Semiconductor device and fabrication thereof
JPS5826178B2 (ja) * 1979-11-30 1983-06-01 株式会社東芝 半導体装置
JPS571253A (en) * 1980-08-04 1982-01-06 Nec Corp Integrated circuit
JPS5762556A (en) * 1980-10-01 1982-04-15 Nec Corp Semiconductor device
JPS57190343A (en) * 1981-05-20 1982-11-22 Hitachi Ltd Semiconductor integrated circuit
JPS58139445A (ja) * 1982-02-15 1983-08-18 Nec Corp 半導体集積回路装置
JPS58219747A (ja) * 1982-06-14 1983-12-21 Nec Corp マスタスライス型半導体装置
JPS594138A (ja) * 1982-06-30 1984-01-10 Nec Corp マスタスライス集積回路装置
JPS59117236A (ja) * 1982-12-24 1984-07-06 Hitachi Ltd 半導体装置
JPS59138349A (ja) * 1983-01-27 1984-08-08 Nippon Telegr & Teleph Corp <Ntt> 多層配線構造
JPS59161049A (ja) * 1983-03-04 1984-09-11 Hitachi Micro Comput Eng Ltd 多層配線部材とその製造方法
JPS59188143A (ja) * 1983-04-08 1984-10-25 Hitachi Ltd 多層配線部材およびその製造方法

Also Published As

Publication number Publication date
EP0182222B1 (de) 1991-06-05
US4716452A (en) 1987-12-29
JPH0644593B2 (ja) 1994-06-08
EP0182222A3 (en) 1987-05-27
JPS61114551A (ja) 1986-06-02
EP0182222A2 (de) 1986-05-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)