KR890008976A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR890008976A
KR890008976A KR1019880015479A KR880015479A KR890008976A KR 890008976 A KR890008976 A KR 890008976A KR 1019880015479 A KR1019880015479 A KR 1019880015479A KR 880015479 A KR880015479 A KR 880015479A KR 890008976 A KR890008976 A KR 890008976A
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South Korea
Prior art keywords
insulating film
wiring pattern
organic
composite
organic insulating
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KR1019880015479A
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English (en)
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KR910009803B1 (ko
Inventor
야스가즈 마세
마사히로 아베
도미에 야마모토
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR890008976A publication Critical patent/KR890008976A/ko
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Publication of KR910009803B1 publication Critical patent/KR910009803B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

내용 없음

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 실시예의 공정 및 구성 설명도.
* 도면의 주요부분에 대한 부호의 설명
11,21 : 열 SiO2가 형성된 반도체기판 12,22 : 제1배선(예를들면 Al-Si)
13,23 : 무기절연막(층간용,예를들면 P-SiN)
14,24 : 유기절연막(층간용,예를들면 PI)
15,25 : 제2배선(예를들면 Al-Si)
16,26 : 무기절연막(표면안정화용,예를들면 P-SiN)
17,27 : 절삭선 19 : 금(crack)
18,28 : 접합패드부 A : 스로우 홀(through hole)
B : 유기절연막 제거부분 C : 패드개공부

Claims (2)

  1. 반도체기판상의 절연막(21)위에 설치된 제1배선패턴(22)과, 이 배선패턴(22) 및 상기 절연막(21)상에 제1무기절연막(23)과 유기절연막(24)의 순서로 적층되어 형성된 복합절연막, 이 복합절연막의 스로우홀(A) 및 그 복합절연막상에 설치된 제2배선패턴(25), 상기 제2배선패턴(25)의 주변부의 일부영역에 설치된 상기 유기절연막(24)의 제거부(B)를 통하여 상기 제1무기절연막(23)상에 직접 설치됨과 더불어 상기 유기절연막(24)상에 설치된 제2무기절연막(26)을 구비하여 구성된 것을 특징으로 하는 반도체장치.
  2. 반도체기판상의 절연막(21)상에 제1배선패턴(22)을 설치하는 공정과, 상기 배선패턴(22) 및 상기 절연막(21)상에 제1무기절연막(23)을 적층하고 그 위에 유기절연막(24)을 적층하여 복합절연막을 설치하는 공정, 상기 복합절연막의 스로우홀(A) 및 그 복합절연막상에 제2배선패턴(25)을 설치하는 공정, 상기 제2배선패턴(25)의 주변부의 일부영역에 상기 유기절연막(24)의 제거부(B)를 그 유기절연막(24)의 스로우홀과 동시에 설치하는 공정, 상기 유기절연막제거부(B)를 통하여 상기 제1무기절연막(23)에 직접 형성되면서 상기 유기절연막(24)상에 형성되는 제2무기절연막(26)을 설치하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880015479A 1987-11-30 1988-11-24 반도체장치 및 그 제조방법 KR910009803B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-302604 1987-11-30
JP62302604A JPH0654774B2 (ja) 1987-11-30 1987-11-30 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR890008976A true KR890008976A (ko) 1989-07-13
KR910009803B1 KR910009803B1 (ko) 1991-11-30

Family

ID=17910980

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880015479A KR910009803B1 (ko) 1987-11-30 1988-11-24 반도체장치 및 그 제조방법

Country Status (5)

Country Link
US (1) US5055906A (ko)
EP (1) EP0318954B1 (ko)
JP (1) JPH0654774B2 (ko)
KR (1) KR910009803B1 (ko)
DE (1) DE3856439T2 (ko)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
GB2279804A (en) * 1993-07-02 1995-01-11 Plessey Semiconductors Ltd Insulating layers for multilayer wiring
US5719065A (en) 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
DE69514588T2 (de) * 1994-07-29 2000-06-21 St Microelectronics Inc Verfahren zum Testen und Reparieren eines integrierten Schaltkreises und zum Herstellen einer Passivierungsstruktur
JPH08162528A (ja) * 1994-10-03 1996-06-21 Sony Corp 半導体装置の層間絶縁膜構造
US5563762A (en) * 1994-11-28 1996-10-08 Northern Telecom Limited Capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit
US5814529A (en) * 1995-01-17 1998-09-29 Semiconductor Energy Laboratory Co., Ltd. Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor
DE19540309A1 (de) * 1995-10-28 1997-04-30 Philips Patentverwaltung Halbleiterbauelement mit Passivierungsaufbau
US6294799B1 (en) * 1995-11-27 2001-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
US5940732A (en) 1995-11-27 1999-08-17 Semiconductor Energy Laboratory Co., Method of fabricating semiconductor device
US7038239B2 (en) 2002-04-09 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
JP3989761B2 (ja) 2002-04-09 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
US7411215B2 (en) 2002-04-15 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same
JP3989763B2 (ja) 2002-04-15 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
US7256421B2 (en) 2002-05-17 2007-08-14 Semiconductor Energy Laboratory, Co., Ltd. Display device having a structure for preventing the deterioration of a light emitting device
JP5118300B2 (ja) * 2005-12-20 2013-01-16 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US20110079908A1 (en) * 2009-10-06 2011-04-07 Unisem Advanced Technologies Sdn. Bhd. Stress buffer to protect device features

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605061B2 (ja) * 1975-09-29 1985-02-08 シチズン時計株式会社 集積化容量素子の製造方法
JPS601846A (ja) * 1983-06-18 1985-01-08 Toshiba Corp 多層配線構造の半導体装置とその製造方法
JPS6030153A (ja) * 1983-07-28 1985-02-15 Toshiba Corp 半導体装置
US4654113A (en) * 1984-02-10 1987-03-31 Fujitsu Limited Process for fabricating a semiconductor device
JPS60206161A (ja) * 1984-03-30 1985-10-17 Toshiba Corp 半導体集積回路
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
JPS6370567A (ja) * 1986-09-12 1988-03-30 Nippon Telegr & Teleph Corp <Ntt> 有機トンネル素子

Also Published As

Publication number Publication date
EP0318954A3 (en) 1989-07-26
US5055906A (en) 1991-10-08
EP0318954A2 (en) 1989-06-07
DE3856439D1 (de) 2000-12-07
EP0318954B1 (en) 2000-11-02
KR910009803B1 (ko) 1991-11-30
DE3856439T2 (de) 2001-03-29
JPH01144632A (ja) 1989-06-06
JPH0654774B2 (ja) 1994-07-20

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