KR870008319A - 반도체 기억회로 - Google Patents

반도체 기억회로 Download PDF

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Publication number
KR870008319A
KR870008319A KR1019860006913A KR860006913A KR870008319A KR 870008319 A KR870008319 A KR 870008319A KR 1019860006913 A KR1019860006913 A KR 1019860006913A KR 860006913 A KR860006913 A KR 860006913A KR 870008319 A KR870008319 A KR 870008319A
Authority
KR
South Korea
Prior art keywords
sense amplifier
circuit
detecting
fets
bit line
Prior art date
Application number
KR1019860006913A
Other languages
English (en)
Other versions
KR900002666B1 (ko
Inventor
요오이찌 도비다
Original Assignee
시기 모리야
미쓰비시 뎅기 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시 뎅기 가부시끼 가이샤 filed Critical 시기 모리야
Publication of KR870008319A publication Critical patent/KR870008319A/ko
Application granted granted Critical
Publication of KR900002666B1 publication Critical patent/KR900002666B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

내용 없음

Description

반도체 기억회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 일 실시예를 표시한 회로도.
제 2 도는 제 1 도의 회로동작을 설명하기 위한 파형도.
제 3 도는 종래의 회로를 표시한 회로도.
* 도면의 주요 부분에 대한 부호 설명
1al~1an, 1bl~1bn ; 메모리셀
1cl~1cn, 1dl~1dn : 더미셀
241~24n : 센스앰프
6a,6b : 워드선
6c,6d : 더미워드선
21a,21b : 디코더 회로, 더미 디코더 회로
32 : 제1의 FET
111~11n, 121~12n: P채널 MOST
141~14n: 제 2의 FET
100 : 평형 제어수단
100a,100b,100c : 제1, 제2, 제 3의 제어회로

Claims (2)

1개의 비트선에 접속된 복수의 메모리셀 및 적어도 1개의 더미셀과 당해 비트선대의 일단에 접속된 센스앰프가 복수로 배치되어서 된 메모리회로와 상기 1쌍의 비트선마다 설치되어 비트선간의 전위를 평형화하기 위한 복수의 FET와, 상기 더미셀을 제어하기 위한 적어도 2개의 더미워드선의 선택이 종료한 것을 검출하고 당해 검출시 상기 복수의 FET를 동작시키는 평형제어 수단과 구비한 것을 특징으로 하는 반도체 기억회로.
제 1 항에 있어서, 상기 평형 제어수단은 상기 더미워드선 단부의 전압이 소정전위로 된 것을 검출하는 제 1 의 제어회로와 상기 센스앰프의 제어신호를 발생하고 상기 소정전위 검출시에 당해 센스앰프의 센스동작을 정지시키는 제 2 의 제어회로와 당해 센스 동작 종료시에 상기 복수의 FET 및 비트선 프리챠지용 FET를 동작하게 하는 제 3 의 제어회로를 구비한 것을 특징으로 하는 반도체 기억회로.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860006913A 1986-02-25 1986-08-21 반도체 기억회로 KR900002666B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP39390 1986-02-25
JP61039390A JPS62197990A (ja) 1986-02-25 1986-02-25 半導体記憶回路
JP61-39390 1988-02-25

Publications (2)

Publication Number Publication Date
KR870008319A true KR870008319A (ko) 1987-09-25
KR900002666B1 KR900002666B1 (ko) 1990-04-21

Family

ID=12551676

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860006913A KR900002666B1 (ko) 1986-02-25 1986-08-21 반도체 기억회로

Country Status (4)

Country Link
US (1) US4792928A (ko)
JP (1) JPS62197990A (ko)
KR (1) KR900002666B1 (ko)
DE (1) DE3705875A1 (ko)

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* Cited by examiner, † Cited by third party
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JPH0682520B2 (ja) * 1987-07-31 1994-10-19 株式会社東芝 半導体メモリ
JPH0194592A (ja) * 1987-10-06 1989-04-13 Fujitsu Ltd 半導体メモリ
JPH07107798B2 (ja) * 1987-11-18 1995-11-15 三菱電機株式会社 ダイナミックランダムアクセスメモリにおけるセンスアンプ駆動装置およびセンスアンプ駆動方法
JP2691280B2 (ja) * 1988-05-12 1997-12-17 三菱電機株式会社 半導体記憶装置
US4975877A (en) * 1988-10-20 1990-12-04 Logic Devices Incorporated Static semiconductor memory with improved write recovery and column address circuitry
US5185721A (en) * 1988-10-31 1993-02-09 Texas Instruments Incorporated Charge-retaining signal boosting circuit and method
JPH02201797A (ja) * 1989-01-31 1990-08-09 Toshiba Corp 半導体メモリ装置
US5093654A (en) * 1989-05-17 1992-03-03 Eldec Corporation Thin-film electroluminescent display power supply system for providing regulated write voltages
KR940007000B1 (ko) * 1991-05-24 1994-08-03 삼성전자 주식회사 개선된 라이트 동작을 가지는 반도체 메모리 장치
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
JPH0757475A (ja) * 1993-08-09 1995-03-03 Nec Corp 半導体メモリ集積回路装置
US5465232A (en) * 1994-07-15 1995-11-07 Micron Semiconductor, Inc. Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory
EP0798729B1 (en) * 1996-03-29 2004-11-03 STMicroelectronics S.r.l. Reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders
US6626901B1 (en) * 1997-03-05 2003-09-30 The Trustees Of Columbia University In The City Of New York Electrothermal instrument for sealing and joining or cutting tissue
JP3327250B2 (ja) 1999-05-14 2002-09-24 日本電気株式会社 半導体記憶装置
KR100454259B1 (ko) * 2001-11-02 2004-10-26 주식회사 하이닉스반도체 모니터링회로를 가지는 반도체메모리장치
US7746717B1 (en) 2007-09-07 2010-06-29 Xilinx, Inc. Desensitizing static random access memory (SRAM) to process variation
US9236102B2 (en) 2012-10-12 2016-01-12 Micron Technology, Inc. Apparatuses, circuits, and methods for biasing signal lines
US9042190B2 (en) 2013-02-25 2015-05-26 Micron Technology, Inc. Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase
US9672875B2 (en) 2014-01-27 2017-06-06 Micron Technology, Inc. Methods and apparatuses for providing a program voltage responsive to a voltage determination
KR102395535B1 (ko) * 2017-11-20 2022-05-10 에스케이하이닉스 주식회사 테스트 회로 블록, 이를 포함하는 저항 변화 메모리 장치 및 저항 변화 메모리 장치의 형성방법

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US3962686A (en) * 1972-05-16 1976-06-08 Nippon Electric Company Limited Memory circuit
US4247917A (en) * 1979-08-27 1981-01-27 Intel Corporation MOS Random-access memory
JPS5942399B2 (ja) * 1979-12-21 1984-10-15 株式会社日立製作所 メモリ装置
US4342102A (en) * 1980-06-18 1982-07-27 Signetics Corporation Semiconductor memory array
US4363111A (en) * 1980-10-06 1982-12-07 Heightley John D Dummy cell arrangement for an MOS memory
JPS5838873B2 (ja) * 1980-10-15 1983-08-25 富士通株式会社 センス回路
JPS601712B2 (ja) * 1980-12-04 1985-01-17 株式会社東芝 半導体記憶装置
US4393475A (en) * 1981-01-27 1983-07-12 Texas Instruments Incorporated Non-volatile semiconductor memory and the testing method for the same
JPS57127989A (en) * 1981-02-02 1982-08-09 Hitachi Ltd Mos static type ram
JPS57195387A (en) * 1981-05-27 1982-12-01 Hitachi Ltd Data lien precharging system of memory integrated circuit
JPS5812193A (ja) * 1981-07-15 1983-01-24 Toshiba Corp 半導体メモリ
JPS5856287A (ja) * 1981-09-29 1983-04-02 Nec Corp 半導体回路
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
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Also Published As

Publication number Publication date
DE3705875A1 (de) 1987-08-27
DE3705875C2 (ko) 1990-09-27
US4792928A (en) 1988-12-20
KR900002666B1 (ko) 1990-04-21
JPS62197990A (ja) 1987-09-01
JPH0568798B2 (ko) 1993-09-29

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