KR20140117285A - 반도체 장치의 제조 방법 및 반도체 장치 - Google Patents

반도체 장치의 제조 방법 및 반도체 장치 Download PDF

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Publication number
KR20140117285A
KR20140117285A KR20140032580A KR20140032580A KR20140117285A KR 20140117285 A KR20140117285 A KR 20140117285A KR 20140032580 A KR20140032580 A KR 20140032580A KR 20140032580 A KR20140032580 A KR 20140032580A KR 20140117285 A KR20140117285 A KR 20140117285A
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South Korea
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semiconductor chip
chip
alignment mark
main surface
semiconductor
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KR20140032580A
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English (en)
Korean (ko)
Inventor
노부히로 기노시따
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르네사스 일렉트로닉스 가부시키가이샤
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Publication of KR20140117285A publication Critical patent/KR20140117285A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR20140032580A 2013-03-22 2014-03-20 반도체 장치의 제조 방법 및 반도체 장치 Abandoned KR20140117285A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013061087A JP6207190B2 (ja) 2013-03-22 2013-03-22 半導体装置の製造方法
JPJP-P-2013-061087 2013-03-22

Publications (1)

Publication Number Publication Date
KR20140117285A true KR20140117285A (ko) 2014-10-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR20140032580A Abandoned KR20140117285A (ko) 2013-03-22 2014-03-20 반도체 장치의 제조 방법 및 반도체 장치

Country Status (5)

Country Link
US (2) US9117826B2 (https=)
JP (1) JP6207190B2 (https=)
KR (1) KR20140117285A (https=)
CN (1) CN104064479B (https=)
TW (1) TWI596714B (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190079788A (ko) * 2017-12-28 2019-07-08 삼성전자주식회사 팬-아웃 반도체 패키지
KR20200020563A (ko) * 2018-08-16 2020-02-26 삼성전자주식회사 수동부품 내장기판
US10998247B2 (en) 2018-08-16 2021-05-04 Samsung Electronics Co., Ltd. Board with embedded passive component
US11021634B2 (en) 2015-09-23 2021-06-01 Lg Chem, Ltd. Adhesive film, preparation method of semiconductor device, and semiconductor device

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JP5876000B2 (ja) * 2012-06-11 2016-03-02 株式会社新川 ボンディング装置およびボンディング方法
KR102149150B1 (ko) * 2013-10-21 2020-08-28 삼성전자주식회사 전자 장치
JP6363854B2 (ja) * 2014-03-11 2018-07-25 キヤノン株式会社 形成方法、および物品の製造方法
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
US9953963B2 (en) * 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
DE102018133319A1 (de) * 2018-12-21 2020-06-25 Rittal Gmbh & Co. Kg Verfahren zur robotergestützten Verdrahtung von elektrischen Komponenten einer auf einer Montageplatte angeordneten elektrischen Schaltanlage
JP7120521B2 (ja) * 2018-12-25 2022-08-17 住友電工デバイス・イノベーション株式会社 電子部品の製造方法及び半導体装置の製造方法
US11430909B2 (en) 2019-07-31 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. BSI chip with backside alignment mark
KR102728190B1 (ko) * 2019-09-10 2024-11-08 삼성전자주식회사 Pop 형태의 반도체 패키지
KR102739235B1 (ko) * 2019-09-24 2024-12-05 삼성전자주식회사 반도체 패키지
KR102766659B1 (ko) * 2020-05-20 2025-02-12 에스케이하이닉스 주식회사 코어 다이가 제어 다이에 스택된 스택 패키지
CN113889420B (zh) * 2020-07-03 2025-05-02 联华电子股份有限公司 半导体元件结构及接合二基板的方法
KR102914869B1 (ko) * 2020-12-16 2026-01-16 삼성전자 주식회사 자주형 ncf 시트 및 그를 포함하는 반도체 패키지
KR102822141B1 (ko) 2021-09-24 2025-06-18 삼성전자주식회사 정렬 검사용 광학 어셈블리, 이를 포함한 광학 장치, 다이 본딩 시스템 및 이를 이용한 다이 본딩 방법
KR20230083102A (ko) * 2021-12-02 2023-06-09 삼성전자주식회사 인쇄회로기판 및 이를 포함하는 반도체 패키지
TWI822230B (zh) * 2022-08-05 2023-11-11 友達光電股份有限公司 發光面板
CN118676109B (zh) * 2024-08-21 2024-11-19 芯爱科技(南京)有限公司 封装基板及其制法

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JP3565319B2 (ja) * 1999-04-14 2004-09-15 シャープ株式会社 半導体装置及びその製造方法
JP2001217387A (ja) * 2000-02-03 2001-08-10 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2002110742A (ja) * 2000-10-02 2002-04-12 Hitachi Ltd 半導体装置の製造方法および半導体製造装置
WO2002082540A1 (en) * 2001-03-30 2002-10-17 Fujitsu Limited Semiconductor device, method of manufacture thereof, and semiconductor substrate
KR100580635B1 (ko) * 2003-12-30 2006-05-16 삼성전자주식회사 전자소자 및 그 제조방법
JP4467318B2 (ja) * 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP2008109115A (ja) * 2006-09-26 2008-05-08 Sekisui Chem Co Ltd 半導体チップ積層体及びその製造方法
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11021634B2 (en) 2015-09-23 2021-06-01 Lg Chem, Ltd. Adhesive film, preparation method of semiconductor device, and semiconductor device
KR20190079788A (ko) * 2017-12-28 2019-07-08 삼성전자주식회사 팬-아웃 반도체 패키지
US10347584B1 (en) 2017-12-28 2019-07-09 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR20200020563A (ko) * 2018-08-16 2020-02-26 삼성전자주식회사 수동부품 내장기판
US10998247B2 (en) 2018-08-16 2021-05-04 Samsung Electronics Co., Ltd. Board with embedded passive component

Also Published As

Publication number Publication date
JP2014187184A (ja) 2014-10-02
JP6207190B2 (ja) 2017-10-04
CN104064479B (zh) 2018-05-15
TW201445681A (zh) 2014-12-01
US20140284780A1 (en) 2014-09-25
US20150325528A1 (en) 2015-11-12
TWI596714B (zh) 2017-08-21
CN104064479A (zh) 2014-09-24
US9117826B2 (en) 2015-08-25
HK1198562A1 (en) 2015-05-15

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